Data alignment over multiple physical lanes
View Patent ↗High speed communication networks divide data traffic into multiple physical lanes. For example, the IEEE standard 40 G/100 G supports sending Ethernet frames at 40/100 gigabits per second over multiple 10/25 Gb/s lanes. Techniques are disclosed for aligning the data across the physical lanes.
1. A method comprising:
receiving a first alignment marker for a first communication lane;
determining a number of symbol errors in the first alignment marker;
comparing the number of symbol errors in the first alignment marker to a lock threshold; and
responsive to the comparison, determining whether to check a second alignment marker received from the first communication lane.
2. The method of claim 1 where determining whether to lock comprises:
determining to lock when the number of symbol errors meets the lock threshold.
3. The method of claim 1 where determining the number of symbol errors in first alignment marker comprises analyzing symbols in first alignment marker against a predefined data pattern.
4. The method of claim 3 , where the predefined data pattern comprises a marker pattern.
5. The method of claim 4 , where the marker pattern comprises a virtual lane marker pattern.
6. The method of claim 3 , where comparing the number of symbol errors in the data to the lock threshold comprises:
tolerating a pre-defined number of the symbol errors in declaring a match to the predefined data pattern.
7. The method of claim 1 , where determining whether to lock comprises:
matching a pre-defined number of consecutive data patterns.
8. The method of claim 7 , further comprising:
reading alignment parameters that specify the pre-defined number of consecutive data patterns.
9. The method of claim 1 , where determining whether to lock comprises:
matching a pre-defined number of consecutive data patterns within a communication block in the data.
10. The method of claim 9 , where the communication block comprises a Forward Error Correcting (FEC) block.
11. A device comprising:
a communication interface configured to receive data for a first communication lane, the data comprising an error correction block, the error correction block comprising a first alignment marker and a second alignment marker; and
circuitry in communication with the communication interface, the circuitry configured to:
compare symbols in the first alignment against a predefined pattern to determine a first number of symbol errors;
compare symbols in the second alignment marker against the predefined pattern to determine a second number of symbols errors;
determine whether to lock based on the comparisons; and
responsive to the determination, lock on the first communication lane when the first number of symbol errors is below a lock threshold and the second number of symbol errors is below the lock threshold.
12. The device of claim 11 , where the predefined pattern comprises a virtual lane pattern.
13. The device of claim 11 , where the circuitry is configured, during the comparison, to tolerate a pre-defined number of symbol errors while still finding a match against the predefined pattern.
14. A receiver comprising:
an input data buffer configured to hold data received over a first communication lane; and
alignment circuitry configured to:
treat a marker pattern as four-bit symbols;
attempt a match of the marker pattern against the data, and determine a number of symbol errors in the match;
when there are fewer than four symbol errors, determine that the match was successful; and
when two consecutive matches are found, determine that a lock has been achieved.
15. The receiver of claim 14 , where:
the two consecutive matches bridge two different Forward Error Correcting (FEC) blocks in the data.
16. The receiver of claim 14 , where:
the alignment circuitry performs marker pattern matching on a basis of symbols across four communication lanes, including the first communication lane, using data obtained from the four communication lanes.
17. The device of claim 11 , wherein the first and second alignment markers comprise consecutive alignment markers within the first communication lane.
18. The device of claim 11 , wherein the error correction block comprises a forward error correction block.
19. The device of claim 11 , wherein the circuitry is further configured to remain out-of-lock when the first number of symbol errors is below a lock threshold and the second number of symbol errors is above the lock threshold.
20. The device of claim 11 , wherein the predefined pattern comprises a virtual lane pattern assigned to the first communication lane.