IP Library Granted Patent US 8,778,756
Granted Patent B2
US 8,778,756 · App. 13/657,362 · Granted Jul 15, 2014

Semiconductor device and method of manufacturing the same

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Quick Facts
Patent No.
US 8,778,756
App. No.
13/657,362
Granted
Jul 15, 2014
Kind
B2
Abstract

A method of manufacturing a semiconductor device comprising the steps of: forming a first interlayer insulating film over a substrate; forming a first conductive film over the first interlayer insulating film; forming a ferroelectric film on the first conductive film; forming a second conductive film on the ferroelectric film; forming an upper electrode of a capacitor by patterning the second conductive film; forming a capacitor dielectric film by patterning the ferroelectric film; and forming a lower electrode of the capacitor by patterning the first conductive film, wherein forming the first conductive film includes: forming a lower conductive layer made of a noble metal other than iridium over the first interlayer insulating film; and forming an upper conductive layer on the lower conductive layer, the upper conductive layer being made of a conductive material, which is different from a material for the lower conductive layer, and which is other than platinum.

Claims (45)

1. A method of manufacturing a semiconductor device, comprising the steps of:

forming a first interlayer insulating film over a semiconductor substrate;

forming a first conductive film over the first interlayer insulating film;

forming a ferroelectric film on the first conductive film;

forming a second conductive film on the ferroelectric film;

forming an upper electrode of a capacitor by patterning the second conductive film;

forming a capacitor dielectric film by patterning the ferroelectric film; and

forming a lower electrode of the capacitor by patterning the first conductive film, wherein the step of forming the first conductive film comprises the steps of:

forming a lower conductive layer made of a noble metal other than iridium over the first interlayer insulating film; and

forming an upper conductive layer on the lower conductive layer, the upper conductive layer being made of a conductive material, which is different from a material for the lower conductive layer, and which is other than platinum; and

further comprising the steps of:

forming a first impurity diffusion region and a second impurity diffusion region in the semiconductor substrate;

forming a first hole in the first interlayer insulating film over the first impurity diffusion region; and

forming a first conductive plug in the first hole,

wherein, in the step of forming the lower electrode, the lower electrode is formed over the first conductive plug, and the lower electrode and the first conductive plug are electrically connected to each other;

forming an underlying insulating film on the first interlayer insulating film and the first conductive plug;

forming a second hole in the underlying insulating film on the first conductive plug;

forming a second conductive plug in the second hole, the second conductive plug being electrically connected to the first conductive plug;

forming a crystalline conductive film on the underlying insulating film and the second conductive plug; and

forming a conductive oxygen barrier film on the crystalline conductive film,

wherein, in the step of forming the first conductive film, the first conductive film is formed on the conductive oxygen barrier film.

2. The method according to claim 1 , wherein

in the step of forming the lower conductive layer, the lower conductive layer is formed thicker than the upper conductive layer.

3. The method according to claim 1 , wherein

in the step of forming the lower conductive layer, a platinum film is formed as the lower conductive layer by sputtering at a substrate temperature of not less than 250° C. nor more than 450° C., and

in the step of forming the upper conductive layer, an iridium film is formed as the upper conductive layer by sputtering at a substrate temperature of not less than 400° C. nor more than 550° C.

4. The method according to claim 1 , wherein

after the upper conductive layer is formed, the first conductive film is annealed in an inert gas atmosphere.

5. The method according to claim 1 , wherein

any one of platinum, rhodium and palladium is employed as the noble metal constituting the lower conductive layer.

6. The method according to claim 1 , wherein

any one of iridium, ruthenium, iridium oxide, ruthenium oxide and SrRuO 3 is employed as the conductive material constituting the upper conductive layer.

7. The method according to claim 1 , further comprising the steps of:

after forming the second conductive plug, forming a planarization conductive film on the second conductive plug and the underlying insulating film; and

planarizing the planarization conductive film,

wherein, in the step of forming the crystalline conductive film, the crystalline conductive film is formed on the planarization conductive film.

8. The method according to claim 1 , further comprising the steps of:

forming a third hole in the first interlayer insulating film over the second impurity diffusion region;

forming a third conductive plug in the third hole;

before forming the underlying insulating film, forming an anti-oxidation insulating film, in which the second hole is to be formed, on the first interlayer insulating film, the first conductive plug and the third conductive plug;

after forming the capacitor, forming a second interlayer insulating film covering the capacitor;

forming a fourth hole in the anti-oxidation insulating film, the underlying insulating film, and the second interlayer insulating film on the third hole; and

forming a fourth conductive plug in the fourth hole, the fourth conductive plug being electrically connected to the third conductive plug.

9. The method according to claim 1 , wherein

in the step of forming the capacitor dielectric film and the step of forming the lower electrode, the ferroelectric film and the first conductive film are etched using the same mask, and thereby portions of the ferroelectric film and the first conductive film, which are left without being etched in regions not covered with the mask, are formed into the capacitor dielectric film and the lower electrode, respectively.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
Reel/Frame 053195/0249 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2012
From: WANG, WENSHENG
To: FUJITSU LIMITED
Reel/Frame 029541/0549 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2012
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 029541/0623 →
CHANGE OF NAME Recorded Dec 28, 2012
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 029550/0005 →