IGBT die structure with auxiliary P well terminal
View Patent ↗An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce V CE(SAT) , current can also be injected into the terminal during IGBT on time. An IGBT assembly involves the IGBT die structure and an associated current injection/extraction circuit. As appropriate, the circuit injects or extracts current from the terminal depending on whether the IGBT is in a turn on time or is in a turn off time.
1. An Insulated Gate Bipolar Transistor (IGBT) die structure comprising:
a P type substrate layer;
an N type drift layer disposed over the P type substrate layer;
a P type body region that extends into the N type drift layer;
an N type source region that extends into the P type body region;
an auxiliary P type well region that extends into the N type drift layer and that is separated from the P type body region;
a gate;
a first metal terminal, wherein the first metal terminal is coupled to the P type body region and to the N type source region;
a second metal terminal, wherein the second metal terminal is coupled to the gate;
a third metal terminal, wherein the third metal terminal is coupled to the auxiliary P type well region; and
a fourth metal terminal that is coupled to the P type substrate layer.
2. The IGBT die structure of claim 1 , wherein the first metal terminal forms a first part of an upper surface of the IGBT die structure, wherein the second metal terminal forms a second part of the upper surface of the IGBT die structure, and wherein the third metal terminal forms a third part of the upper surface of the IGBT die structure.
3. The IGBT die structure of claim 1 , wherein the IGBT die structure has a substantially planar upper semiconductor surface, wherein the P type body region extends from the substantially planar upper semiconductor surface and into the N type drift layer, wherein the N type source region extends from the substantially planar upper semiconductor surface and into the P type body region, and wherein the auxiliary P type well region extends from the substantially planar upper semiconductor surface and into the N type drift layer.
4. The IGBT die structure of claim 3 , wherein no N type layer both contacts the third metal terminal and also extends from the substantially planar upper semiconductor surface into the auxiliary P type well region.
5. The IGBT die structure of claim 1 , wherein the IGBT die structure comprises an array of IGBT unit cell structures, wherein each of the IGBT unit cell structures has its own auxiliary P type well region, and wherein the third metal terminal is coupled to all the auxiliary P type well regions of all the IGBT unit cell structures.
6. The IGBT die structure of claim 1 , wherein the IGBT die structure further comprises:
an N type buffer layer that is disposed between the N type drift layer and the P type substrate layer.
7. The IGBT die structure of claim 1 , wherein the IGBT die structure comprises an IGBT, wherein the third metal terminal and the auxiliary P type well region are structured such that during a turn on time TON of the IGBT a current can be injected into the IGBT through the third metal terminal resulting in a charge carrier concentration in the N type drift layer being increased, and wherein the third metal terminal and the auxiliary P type well region are structured such that during a turn off time TOFF of the IGBT a current can be extracted out of the IGBT through the third metal terminal resulting in a charge carrier concentration in the N type drift layer being decreased.
8. The IGBT die structure of claim 1 , wherein a portion of the third metal terminal is a bond pad.
9. An Insulated Gate Bipolar Transistor (IGBT) die structure comprising:
an IGBT having a gate, an N type source region, a P type body region, an N type drift layer, and a P type substrate layer, wherein a first metal terminal is coupled to the N type source region and to the P type body region, wherein a second metal terminal is coupled to the gate, and wherein a fourth metal terminal is coupled to the P type substrate layer; and
means for injecting charge carriers into the N type drift layer during a turn on time TON of the IGBT by injecting a current into the IGBT through a third metal terminal of the IGBT.
10. The IGBT die structure of claim 9 , wherein the means comprises the third metal terminal and an auxiliary P type well region, wherein the third metal terminal is coupled to the auxiliary P type well region but is not coupled to any of the first, second and fourth metal terminals, wherein the auxiliary P type well region is separated from the P type body region of the IGBT by an amount of the N type drift layer, and wherein the auxiliary P type well region is separated from the P type substrate layer by an amount of the N type drift layer.
11. The IGBT die structure of claim 10 , wherein the means includes no N type region, and wherein there is no N type region in contact with the third metal terminal.
12. The IGBT die structure of claim 11 , wherein the means is also for extracting charge carriers from the N type drift layer during a turn off time TOFF of the IGBT by extracting a current out of the IGBT through a third metal terminal of the IGBT.
13. An Insulated Gate Bipolar Transistor (IGBT) die structure comprising:
a P type substrate layer;
an N type drift layer disposed over the P type substrate layer;
a P type body region that extends into the N type drift layer;
an N type source region that extends into the P type body region;
an auxiliary P type well region that extends into the N type drift layer and that is separated from the P type body region;
a gate;
a first metal terminal, wherein the first metal terminal is coupled to the P type body region and to the N type source region;
a second metal terminal, wherein the second metal terminal is coupled to the gate;
a third metal terminal, wherein the third metal terminal is coupled to the auxiliary P type well region, and wherein no metal of the third metal terminal is directly contacting any N− type doped portion of the drift layer; and
a fourth metal terminal that is coupled to the P type substrate layer.