Reverse optical proximity correction method
A method for fabricating an anti-fuse memory cell having a semiconductor structure with a minimized area. The method includes providing a reference pattern for the semiconductor structure, and applying a reverse OPC technique that includes inverting selected corners of the reference pattern. The reverse OPC technique uses photolithographic distortions to provide a resulting fabricated pattern that is intentionally distorted relative to the reference pattern. By inverting corners of a geometric reference pattern, the resulting distorted pattern will have an area that is reduced relative to the original reference pattern. This technique is advantageous for reducing the area of a selected region of a semiconductor structure which may otherwise not be possible through normal design parameters.
1. A reverse optical proximity correction (OPC) method, comprising:
providing a reference pattern of a semiconductor structure, the reference pattern being rectangular in shape;
selecting an area of the reference pattern for area reduction by photolithographic distortion;
inverting at least one corner region of the area to form a reverse OPC imaging pattern having an area smaller than the reference pattern; and
fabricating the semiconductor structure having a region corresponding to the at least one corner region being rounded.
2. The reverse optical proximity correction (OPC) method of claim 1 , wherein inverting the at least one corner includes subtracting a predefined rectangular shape from the at least one corner region of the area.
3. The reverse optical proximity correction (OPC) method of claim 1 , wherein selecting includes identifying an anti-fuse transistor programming area.
4. The reverse optical proximity correction (OPC) method of claim 1 , further including manufacturing a mask plate with the reverse OPC imaging pattern.
5. The reverse optical proximity correction (OPC) method of claim 4 , further including fabricating the semiconductor structure using the mask plate in a photolithography process.
6. The reverse optical proximity correction (OPC) method of claim 5 , wherein a resulting fabricated semiconductor structure has a shape that differs substantively from the reference pattern.
7. The reverse optical proximity correction (OPC) method of claim 6 , wherein the reference pattern of the semiconductor structure corresponds to an active area of an anti-fuse transistor of a memory cell.
8. The reverse optical proximity correction (OPC) method of claim 7 , wherein a portion of the active area of the anti-fuse transistor is covered by a thin gate oxide and a thick gate oxide having a thickness greater than the thin gate oxide.
9. The reverse optical proximity correction (OPC) method of claim 8 , wherein the area of the reference pattern corresponds to the thin gate oxide of the anti-fuse transistor.
10. The reverse optical proximity correction (OPC) method of claim 1 , further including applying optical proximity correction to other portions of the reference pattern to correct for photolithographic distortion.