Memory refresh rate throttling for saving idle power

1. A method comprising:

maintaining a threshold value, wherein the threshold value indicates a period of time;

determining that a processor is in any one of a plurality of low power consumption states;

responsive to determining that the processor is in any one of the plurality of low power consumption states, incrementing a counter, wherein the counter indicates the period of time the processor has been in any one of the plurality of low power consumption states;

determining that the counter value is equal to or greater than the threshold value; and

responsive to determining that the counter value is equal to or greater than the threshold value, sending a first indication to a memory module indicating to the memory module to reduce the memory module refresh rate,

wherein determining that the processor is in any one of the plurality of low power consumption states comprises:

reading a first value hosted in a first storage location, wherein the first value hosted in the first storage location indicates a first of the plurality of low power consumption states;

reading a second value hosted in a second storage location, wherein the second value hosted in the second storage location indicates the current power consumption state of the processor, wherein the current power consumption state is any one of the plurality of low power consumptions states; and

comparing the first value hosted in the first storage location with the second value hosted in the second storage location, wherein the comparison can indicate that the processor is in any one of the plurality of low power consumption states.

2. The method of claim 1 , wherein the first storage location comprises a register designated to host a value indicating a first of the plurality of low power consumption states and the second storage location comprises a register designated to host a value indicating the current power consumption state of the processor.

3. The method of claim 1 , wherein the first and the second storage locations comprise at least part of a register designated to host values indicating a first of the plurality of low power consumption states and indicating the current power consumption state of the processor.

4. The method of claim 1 further comprising:

determining that the processor is not in any one of the plurality of low power consumption states; and

responsive to determining that the processor is not in any one of the plurality of low power consumption states, sending a second indication to the memory module indicating to the memory module to increase the memory module refresh rate.

5. The method of claim 1 , wherein the first value hosted in the first storage location indicates a minimum ratio between a clock rate external to the processor and a clock rate internal to the processor and the second value hosted in the second storage location indicates the current ratio between the clock rate external to the processor and the clock rate internal to the processor.

6. A computer program product comprising:

a non-transitory computer readable storage medium having computer usable program code embodied therewith, the computer usable program code comprising a computer usable program code configured to:

maintain a threshold value, wherein the threshold value indicates a period of time;

determine that a processor is in any one of a plurality of low power consumption states;

responsive to a determination that the processor is in any one of the plurality of low power consumption states, increment a counter, wherein the counter indicates the period of time the processor has been in any one of the plurality of low power consumption states;

determine that the counter value is equal to or greater than the threshold value;

responsive to a determination that the counter value is equal to or greater than the threshold value, send a first indication to a memory module indicating to the memory module to reduce the memory module refresh rate; and

determine that a processor is in any one of a plurality of low power consumption states by:

reading a first value hosted in a first storage location, wherein the first value hosted in the first storage location indicates a first of the plurality of low power consumption states;

reading a second value hosted in a second storage location, wherein the second value hosted in the second storage location indicates the current power consumption state of the processor, wherein the current power consumption state is any one of the plurality of low power consumptions states; and

comparing the first value hosted in the first storage location with the second value hosted in the second storage location, wherein the comparison can indicate that the processor is in one of the plurality of low power consumption states.

7. The computer program product of claim 6 , wherein the first storage location comprises a register designated to host a value indicating a first of the plurality of low power consumption states and the second storage location comprises a register designated to host a value indicating the current power consumption state of the processor.

8. The computer program product of claim 6 , wherein the first and the second storage locations comprise at least part of a register designated to host values indicating a first of the plurality of low power consumption states and indicating the current power consumption state of the processor.

9. The computer program product of claim 6 further configured to:

determine that the processor is not in any one of the plurality of low power consumption states; and

responsive to a determination that the processor is not in any one of the plurality of low power consumption states, send a second indication to the memory module indicating to the memory module to increase the memory module refresh rate.

10. The computer program product of claim 6 , wherein the first value hosted in the first storage location indicates a minimum ratio between a clock rate external to the processor and a clock rate internal to the processor and the second value hosted in the second storage location indicates the current ratio between the clock rate external to the processor and the clock rate internal to the processor.

11. An apparatus comprising:

a processor;

a memory module coupled with the processor;

a memory controller coupled with the processor and the memory module, configured to:

maintain a threshold value, wherein the threshold value indicates a period of time;

determine that a processor is in any one of a plurality of low power consumption states;

responsive to a determination that the processor is in any one of the plurality of low power consumption states, increment a counter, wherein the counter indicates the period of time the processor has been in any one of the plurality of low power consumption states;

determine that the counter value is equal to or greater than the threshold value; and

responsive to a determination that the counter value is equal to or greater than the threshold value, send a first indication to a memory module indicating to the memory module to reduce the memory module refresh rate; and

a first storage location designated to host a first value, wherein the first value indicates a first of the plurality of low power consumption states; and

a second storage location designated to host a second value, wherein the second value indicates the current power consumption state of the processor, wherein the current power consumption state of the processor is any one of the plurality of low power consumption states.

12. The apparatus of claim 11 , wherein the memory controller configured to determine that a processor is in any one of the plurality of low power consumption states is configured to:

read the first value hosted in the first storage location;

read the second value hosted in the second storage location; and

compare the first value with the second value, wherein the comparison can indicate that the processor is in any one of the plurality of low power consumption states.

13. The apparatus of claim 11 , wherein the first storage location comprises a first register designated to host a value indicating a first of the plurality of low power consumption states and the second storage location comprises a second register designated to host a value indicating the current power consumption state of the processor.

14. The apparatus of claim 11 , wherein the first and the second storage locations comprise at least part of a register designated to host values indicating a first of the plurality of low power consumption states and indicating the current power consumption state of the processor.

15. The apparatus of claim 11 further comprising a counter designated to host the number of time periods the processor has been in any one of the plurality of low power consumption states.

16. The apparatus of claim 11 , wherein the memory controller is further configured to:

determine that the processor is not in any one of the plurality of low power consumption states; and

responsive to a determination that the processor is not in any one of the plurality of low power consumption states, send a second indication to the memory module indicating to the memory module to increase the memory module refresh rate.

17. The apparatus of claim 11 , wherein the first value hosted in the first storage location indicates a minimum ratio between a clock rate external to the processor and a clock rate internal to the processor and the second value hosted in the second storage location indicates the current ratio between the clock rate external to the processor and the clock rate internal to the processor.