Backplane clock synchronization

1. An apparatus, comprising:

a backplane that includes a clock, wherein the apparatus is configured to generate timestamps periodically based on the clock;

at least one processing element coupled to the clock via the backplane; and

a synchronization interface coupled to or included in the at least one processing element;

wherein the at least one processing element is configured to:

compare a first timestamp received from the clock via the backplane with a second timestamp received from the synchronization interface to determine time error information, wherein the second timestamp is generated based on an external clock;

determine adjustment information based on the time error information; and

synchronize the clock with the external clock using the adjustment information, via the backplane.

2. The apparatus of claim 1 ,

wherein, to synchronize the clock via the backplane, the at least one processing element is configured to send the adjustment information to the backplane via a low pin count system management bus;

wherein the backplane is configured as a PCI Express eXtensions for Instrumentation (PXIe) backplane; and

wherein the at least one processing element is coupled to the synchronization interface via a PCI Express bus.

3. The apparatus of claim 1 ,

wherein the apparatus includes a chassis configured to allow modules to be plugged into the backplane;

wherein an output of the clock is provided via the backplane to one or more modules plugged into the backplane; and

wherein one or more modules plugged into the backplane are configured to use the synchronized clock as a reference clock in order to maintain a shared notion of time.

4. The apparatus of claim 3 ,

wherein the chassis is a PXIe chassis, the backplane is a PXIe backplane, and the one or more modules are PXIe modules.

5. The apparatus of claim 1 ,

wherein the at least one processing element includes a scaling circuit, configured to scale an output of the clock;

wherein the synchronization interface is configured to map an output of the scaling circuit to the second timestamp; and

wherein the at least one processing element is configured to use the mapping to compare the first and second timestamp.

6. The apparatus of claim 1 , wherein the synchronization interface is included in a module plugged into the backplane and is configured to send the second timestamp to the at least one processing element via the backplane.

7. The apparatus of claim 1 , wherein the at least one processing element is included in a module plugged into the backplane and is configured to send the adjustment information via the backplane to synchronize the clock.

8. The apparatus of claim 1 , further comprising:

a calibration digital-to-analog converter;

wherein the at least one processing element is configured to synchronize the clock by sending adjustment information to the calibration digital-to-analog converter and the calibration digital-to-analog converter is configured to convert the adjustment information to a voltage and provide the voltage to control the clock.

9. The apparatus of claim 1 , wherein the at least one processing element is embedded in the apparatus.

10. The apparatus of claim 1 , wherein the at least one processing element is configured to send a trigger signal based on the synchronized clock.

11. The apparatus of claim 1 , wherein the at least one processing element includes:

a phase detector, configured to compare the first and second timestamp.

12. The apparatus of claim 11 , wherein the phase detector is included in the synchronization interface.

13. The apparatus of claim 11 , where the synchronization interface is configured to send the second timestamp to the phase detector via the backplane.

14. The apparatus of claim 1 , wherein the clock is embedded in the backplane.

15. The apparatus of claim 1 , wherein the synchronization interface is configured to receive the second timestamp via a network implementing a time synchronization protocol.

16. The apparatus of claim 1 ,

wherein the at least one processing element is configured to determine an error based on comparing the first and second timestamp; and

wherein the at least one processing element is configured to perform a first operation to determine the adjustment information when the error is greater than a particular threshold and a perform a second operation to determine the adjustment information when the error is smaller than the particular threshold.

17. A method for synchronizing a clock included in a backplane, the method comprising:

receiving, via the backplane, first time information, wherein the time information is generated based on an output clock signal from the clock;

comparing first time information received from the clock via the backplane with second time information received from a synchronization interface;

determining adjustment information based on said comparing; and

synchronizing the clock with an external clock using the adjustment information, via the backplane, wherein the external clock is associated with the second time information.

18. The method of claim 17 , further comprising:

synchronizing an internal clock of a module plugged into the backplane with the clock.

19. The method of claim 17 , further comprising:

sending a trigger signal based on the clock to a module plugged into the backplane.

20. The method of claim 17 , further comprising:

scaling an output of the clock before said comparing.

21. The method of claim 17 , wherein said synchronizing the clock with an external clock includes sending the adjustment information to a digital-to-analog converter.

22. The method of claim 17 , wherein said determining adjustment information based on said comparing includes:

performing a particular operation to determine the adjustment information in response to a difference between the first and second time information being greater than a particular threshold.