Bitwidth reduction in loop filters used for digital PLLS

1. A digital phase locked loop (DPLL), comprising:

a phase frequency detector configured to determine a phase difference between a reference signal and a feedback signal and to convert the phase difference to a digital word;

a digital loop filter configured to filter the digital word to generate a control word;

a bit shift network configured to modify the digital word in a manner that switches a resolution of the digital loop filter between two or more distinct resolution states that comprise a bit sequence located at different positions in the digital word; and

a digitally controlled oscillator (DCO) to receive the control word and to vary the phase of the feedback signal based upon the control word.

2. The DPLL of claim 1 , wherein the bit shift network comprises:

a first bit shifting element located upstream of the digital loop filter and configured to selectively shift a position of bits within the digital word in a first direction by a bit shift value; and

a second bit shifting element located downstream of the digital loop filter and configured to selectively shift the position of bits within the digital word in a second direction, opposite the first direction, by the bit shift value.

3. The DPLL of claim 2 ,

wherein the first bit shifting element is configured to selectively reduce a resolution of the digital loop filter from a first resolution to a second resolution by shifting the position of bits within the digital word in the first direction.

4. The DPLL of claim 3 , further comprising:

a truncation element configured to truncate the shifted digital word to reduce a number of bits in the shifted digital word by a number that is equal to the bit shift value.

5. The DPLL of claim 2 , further comprising:

wherein the first bit shifting element is configured to selectively increase a resolution of the digital loop filter from a first resolution to a second resolution by shifting the position of bits within the digital word in the first direction.

6. The DPLL of claim 2 , further comprising:

a controller configured to generate a switching signal that selectively switches the resolution of the digital loop filter when the digital phase locked loop transitions from a settling state to a settled state.

7. The DPLL of claim 6 , further comprising:

a measurement element configured to measure the phase difference between the reference signal and the feedback signal; and

a comparison element configured to compare the measured phase difference to a predetermined threshold value;

wherein the comparison element is configured to generate a control signal that causes the controller to switch the resolution of the digital loop filter when the phase difference violates the predetermined threshold value.

8. The DPLL of claim 6 , further comprising:

a counter configured to increment a counter value; and

a comparison element configured to compare the counter value to a predetermined threshold value;

wherein the comparison element is configured to generate a control signal that causes the controller to switch the resolution of the digital loop filter when the counter value violates the predetermined threshold value.

9. The DPLL of claim 6 ,

a delay element connected between the controller and the second bit shifting element and configured to introduce a delay into the switching signal that accounts for a delay of the digital loop filter.

10. The DPLL of claim 2 ,

wherein the first bit shifting element comprises a multiplication unit configured to multiply the digital word by a multiplication factor that shifts the position of the bits within the digital word in the first direction; and

wherein the second bit shifting element comprises a division unit configured to divide the digital word by a division factor that shifts the position of the bits within the digital word in the second direction.

11. The DPLL of claim 1 , wherein the digital loop filter comprises:

a lead filter having a multiplexer connected in series with a D-flip flop, wherein the multiplexer comprises a first input connected to the output of the first bit shifting element, and a second input connected to an additional bit shifting element connected to an output of the D-flip flop.

12. A digital phase locked loop (DPLL), comprising:

a phase frequency detector configured to determine a phase difference between a reference signal and a feedback signal and to convert the phase difference to a digital word;

a first bit shifting element configured to selectively shift a position of bits within the digital word in a first direction by a bit shift value;

a digital loop filter configured to filter the digital word that is output from the first bit shifting element to generate a control word;

a second bit shifting element configured to selectively shift the position of bits within the control word in a second direction, opposite the first direction, by a bit shift value;

a digitally controlled oscillator (DCO) to the phase of the feedback signal based upon the control word that is output from the second bit shifting element; and

a controller configured to generate a switching signal that selectively switches a resolution of the digital loop filter when the DPLL transitions from a settling state to a locked state.

13. The DPLL of claim 12 ,

wherein the first bit shifting element is configured to selectively reduce a resolution of the digital loop filter from a first resolution to a second resolution by shifting the position of bits within the digital word in the first direction.

14. The DPLL of claim 12 ,

wherein the first bit shifting element is configured to selectively increase a resolution of the digital loop filter from a first resolution to a second resolution by shifting the position of bits within the digital word in the first direction.

15. The DPLL of claim 12 ,

a measurement element configured to measure the phase difference between the reference signal and the feedback signal; and

a comparison element configured to compare the measured phase difference to a predetermined threshold value;

wherein the comparison element is configured to generate a control signal that causes the controller to switch the resolution of the digital loop filter when the phase difference violates the predetermined threshold value.

16. The DPLL of claim 12 ,

a counter configured to increment a counter value; and

a comparison element configured to compare the counter value to a predetermined threshold value;

wherein the comparison element is configured to generate a control signal that causes the controller to switch the resolution of the digital loop filter when the counter value violates the predetermined threshold value.

17. A method, comprising:

receiving a reference signal;

receiving a feedback signal;

determining a phase difference between the reference signal and the feedback signal and generating a digital word that is proportional to the phase difference;

selectively shifting a position of bits within the digital word in a first direction by a bit shift value to generate a shifted digital word;

providing the shifted digital word to a digital loop filter to generate control word; and

selectively shifting the position of bits within the control word in a second direction by the bit shift value opposite the first direction to generate a shifted control word.

18. The method of claim 17 ,

wherein selectively shifting the position of bits within the digital word in the first direction reduces a resolution of the digital loop filter from a first resolution to a second resolution.

19. The method of claim 17 ,

wherein selectively shifting the position of bits within the digital word in the first direction increases a resolution of the digital loop filter from a first resolution to a second resolution.

20. The method of claim 17 , further comprising:

truncating the shifted digital word to reduce a number of bits in the shifted digital word by a number that is equal to the bit shift value.