Level shifter circuit, scanning circuit, display device and electronic equipment

1. A level shifter circuit,

wherein a first transistor circuit configured of a first conductive type transistor and a second transistor circuit configured of a second conductive type transistor are connected serially between a first fixed power source and a second fixed power source, and a third transistor circuit configured of the first conductive type transistor and a fourth transistor circuit configured of the second conductive type transistor are connected serially between the first fixed power source and the second fixed power source;

wherein a first input voltage is applied to an input terminal of the second transistor circuit and a second input voltage is applied to an input terminal of the fourth transistor circuit;

wherein an input terminal of the first transistor circuit is connected to an output terminal of the third and the fourth transistor circuits, and an input terminal of the third transistor circuit is connected to an output terminal of the first and the second transistor circuits;

wherein two transistor circuits of at least one side of two transistor circuits of a first fixed power source side and two transistor circuits of a second fixed power source side are configured of double gate transistors; and

wherein the level shifter circuit has a switch element for applying a voltage of a third fixed power source to a common connection node of the double gate transistor of two transistor circuits of the power source side of the other side when two transistor circuits of the power source side of one side are in an operating state, and

wherein the voltage of the third fixed sower source has a value between voltages of the first fixed power source and the second fixed power source.

2. The level shifter circuit according to claim 1 ,

wherein the voltage between the first fixed power source and the third fixed power source, and the voltage between the third fixed power source and the second fixed power source are voltages within a range of a source-drain withstand voltage of each transistor constituting the first to the fourth transistor circuits.

3. The level shifter circuit according to claim 1 ,

wherein the first input voltage and the second input voltage are reverse phased voltages to each other.

4. The level shifter circuit according to claim 1 ,

wherein the voltage of the third fixed power source is an average value of respective voltages of the first fixed power source and the second fixed power source.

5. The level shifter circuit according to claim 1 ,

wherein the switch element is a transistor having the same conductive type as the transistor constituting two transistor circuits of the power source side of the other side.

6. The level shifter circuit according to claim 1 ,

wherein an inverter circuit of the final stage is connected to the common connection node of the third and the fourth transistor circuits.

7. The level shifter circuit according to claim 1 ,

wherein the first fixed power source is a positive side power source and second fixed power source is a negative side power source, and

the first conductive type transistor is a P channel type transistor and the second conductive type transistor is an N channel type transistor.

8. The level shifter circuit according to claim 7 ,

wherein the voltage of the first fixed power source is higher than the voltage of a high voltage side of the first and the second input voltages, and

the voltage of the second fixed power source is lower than or equal to the voltage of a low voltage side of the first and the second input voltages.

9. The level shifter circuit according to claim 1 ,

wherein the first fixed power source is the negative side power source and the second fixed power source is the positive side power source, and

the first conductive type transistor is the N channel type transistor and the second conductive type transistor is the P channel type transistor.

10. The level shifter circuit according to claim 9 ,

wherein the voltage of the first fixed power source is lower than the voltage of the low voltage side of the first and the second input voltages, and

the voltage of the second fixed power source is higher than or equal to the voltage of the high voltage side of the first and the second input voltages.

11. A scanning circuit comprising a level shifter circuit according to claim 1 , and further comprising:

an inverter circuit in a final stage, the level shifter circuit being in a preceding stage of the inverter circuit.

12. A display device comprising a level shifter circuit according to claim 1 , and further comprising:

a pixel array unit where the pixels including an electro-optic element are arranged in a matrix; and

a scanning circuit which has an inverter circuit in a final stage and the level shifter circuit in a preceding stage of the inverter circuit, and scans each pixel of the pixel array unit.

13. Electronic equipment comprising a level shifter circuit according to claim 1 , and further comprising:

a display device including:

a pixel array unit where the pixels including an electro-optic element are arranged in a matrix; and

a scanning circuit which has an inverter circuit in a final stage and the level shifter circuit in a preceding stage of the inverter circuit, and scans each pixel of the pixel array unit.

14. A level shifter circuit,

wherein a first transistor circuit configured of a first conductive type transistor and a second transistor circuit configured of a second conductive type transistor are connected serially between a first fixed power source and a second fixed power source, and a third transistor circuit configured of the first conductive type transistor and a fourth transistor circuit configured of the second conductive type transistor are connected serially between the first fixed power source and the second fixed power source;

wherein a first input voltage is applied to an input terminal of the second transistor circuit and a second input voltage is applied to an input terminal of the fourth transistor circuit;

wherein an input terminal of the first transistor circuit is connected to an output terminal of the third and the fourth transistor circuits, and an input terminal of the third transistor circuit is connected to an output terminal of the first and the second transistor circuits;

wherein two transistor circuits of at least one side of two transistor circuits of a first fixed power source side and two transistor circuits of a second fixed power source side are configured of double gate transistors; and

wherein the level shifter circuit has a switch element for applying a voltage of a third fixed power source to a common connection node of the double ate transistor of two transistor circuits of the power source side of the other side when two transistor circuits of the power source side of one side are in an operating state, and

wherein the switch element has the first input voltage or the second input voltage as a gate input.

15. A scanning circuit comprising a level shifter circuit according to claim 14 , and further comprising:

an inverter circuit in a final stage, the level shifter circuit being in a preceding stage of the inverter circuit.

16. A display device comprising a level shifter circuit according to claim 14 , and further comprising:

a pixel array unit where the pixels including an electro-optic element are arranged in a matrix; and

a scanning circuit which has an inverter circuit in a final stage and the level shifter circuit in a preceding stage of the inverter circuit, and scans each pixel of the pixel array unit.

17. Electronic equipment comprising a level shifter circuit according to claim 14 , and further comprising:

a display device including:

a pixel array unit where the pixels including an electro-optic element are arranged in a matrix; and

a scanning circuit which has an inverter circuit in a final stage and the level shifter circuit in a preceding stage of the inverter circuit, and scans each pixel of the pixel array unit.

18. A level shifter circuit,

wherein a first transistor circuit configured of a first conductive t me transistor and a second transistor circuit configured of a second conductive type transistor are connected serially between a first fixed power source and a second fixed power source, and a third transistor circuit configured of the first conductive type transistor and a fourth transistor circuit configured of the second conductive type transistor are connected serially between the first fixed power source and the second fixed power source;

wherein a first input voltage is applied to an input terminal of the second transistor circuit and a second input voltage is applied to an input terminal of the fourth transistor circuit;

wherein an input terminal of the first transistor circuit is connected to an output terminal of the third and the fourth transistor circuits, and an input terminal of the third transistor circuit is connected to an output terminal of the first and the second transistor circuits;

wherein two transistor circuits of at least one side of two transistor circuits of a first fixed power source side and two transistor circuits of a second fixed power source side are configured of double gate transistors; and

wherein the level shifter circuit has a switch element for applying a voltage of a third fixed power source to a common connection node of the double gate transistor of two transistor circuits of the power source side of the other side when two transistor circuits of the power source side of one side are in an operating state,

wherein the first fixed power source is a positive side power source and second fixed power source is a negative side power source, and

the first conductive type transistor is a P channel type transistor and the second conductive type transistor is an N channel type transistor, and

wherein the voltage of the first fixed power source is higher than the voltage of the positive side power source of the inverter circuit of the final stage, and

the voltage of the second fixed power source is the same as the voltage of the negative side power source of the inverter circuit of the final stage.

19. A scanning circuit comprising a level shifter circuit according to claim 18 , and further comprising:

an inverter circuit in a final stage, the level shifter circuit being in a preceding stage of the inverter circuit.

20. A display device comprising a level shifter circuit according to claim 18 , and further comprising:

a pixel array unit where the pixels including an electro-optic element are arranged in a matrix; and

a scanning circuit which has an inverter circuit in a final stage and the level shifter circuit in a preceding stage of the inverter circuit, and scans each pixel of the pixel array unit.

21. Electronic equipment comprising a level shifter circuit according to claim 18 , and further comprising:

a display device including:

a pixel array unit where the pixels including an electro-optic element are arranged in a matrix; and

a scanning circuit which has an inverter circuit in a final stage and the level shifter circuit in a preceding stage of the inverter circuit, and scans each pixel of the pixel array unit.

22. A level shifter circuit,

wherein a first transistor circuit configured of a first conductive type transistor and a second transistor circuit configured of a second conductive type transistor are connected serially between a first fixed power source and a second fixed power source, and a third transistor circuit configured of the first conductive type transistor and a fourth transistor circuit configured of the second conductive type transistor are connected serially between the first fixed power source and the second fixed power source;

wherein a first input voltage is applied to an input terminal of the second transistor circuit and a second input voltage is applied to an input terminal of the fourth transistor circuit;

wherein an input terminal of the first transistor circuit is connected to an output terminal of the third and the fourth transistor circuits, and an input terminal of the third transistor circuit is connected to an output terminal of the first and the second transistor circuits;

wherein two transistor circuits of at least one side of two transistor circuits of a first fixed power source side and two transistor circuits of a second fixed power source side are configured of double gate transistors; and

wherein the level shifter circuit has a switch element for applying a voltage of a third fixed power source to a common connection node of the double ate transistor of two transistor circuits of the power source side of the other side when two transistor circuits of the power source side of one side are in an operating state, and

wherein the first fixed power source is the negative side power source and the second fixed power source is the positive side power source, and

the first conductive type transistor is the N channel type transistor and the second conductive type transistor is the P channel type transistor, and

wherein the voltage of the first fixed power source is lower than the voltage of the negative side power source of the inverter circuit of the final stage, and

the voltage of the second fixed power source is the same as the voltage of the positive side power source of the inverter circuit of the final stage.

23. A scanning circuit comprising a level shifter circuit according to claim 22 , and further comprising:

an inverter circuit in a final stage, the level shifter circuit being in a preceding stage of the inverter circuit.

24. A display device comprising a level shifter circuit according to claim 22 , and further comprising:

a pixel array unit where the pixels including an electro-optic element are arranged in a matrix; and

a scanning circuit which has an inverter circuit in a final stage and the level shifter circuit in a preceding stage of the inverter circuit, and scans each pixel of the pixel array unit.

25. Electronic equipment comprising a level shifter circuit according to claim 22 , and further comprising:

a display device including:

a pixel array unit where the pixels including an electro-optic element are arranged in a matrix; and

a scanning circuit which has an inverter circuit in a final stage and the level shifter circuit in a preceding stage of the inverter circuit, and scans each pixel of the pixel array unit.