IP Library Granted Patent US 8,796,779
Granted Patent B2
US 8,796,779 · App. 13/665,305 · Granted Aug 5, 2014

Semiconductor device

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Quick Facts
Patent No.
US 8,796,779
App. No.
13/665,305
Granted
Aug 5, 2014
Kind
B2
Abstract

A first MIS transistor and a second MIS transistor of the same conductivity type are formed on an identical semiconductor substrate. An interface layer included in a gate insulating film of the first MIS transistor has a thickness larger than that of an interface layer included in a gate insulating film of the second MIS transistor.

Claims (41)

1. A semiconductor device comprising:

a first MIS transistor and a second MIS transistor of an identical conductivity type provided on an identical semiconductor substrate,

wherein the first MIS transistor includes a first gate insulating film formed on a first active region in the semiconductor substrate and a first gate electrode formed on the first gate insulating film,

the second MIS transistor includes a second gate insulating film formed on a second active region in the semiconductor substrate and a second gate electrode formed on the second gate insulating film,

the first gate insulating film includes a first interface layer being in contact with the semiconductor substrate and a first high dielectric constant insulating film formed on the first interface layer,

the second gate insulating film includes a second interface layer being in contact with the semiconductor substrate and a second high dielectric constant insulating film formed on the second interface layer,

the first interface layer has a thickness larger than that of the second interface layer, and

each of the first interface layer and the second interface layer is made of a silicon dioxide film or a silicon oxynitride film.

2. The semiconductor device of claim 1 , wherein

the first gate electrode includes first sidewall spacers formed on side surfaces thereof and first insulating spacers interposed between the first gate electrode and the first sidewall spacers,

the second gate electrode includes second sidewall spacers formed on side surfaces thereof and second insulating spacers interposed between the second gate electrode and the second sidewall spacers, and

the first insulating spacers are thinner than the second insulating spacers.

3. The semiconductor device of claim 2 ,

the first insulting spacers are offset spacers each having an I-shaped cross section, and

the second insulating spacers are underlying spacers each having an L-shaped cross section.

4. The semiconductor device of claim 2 , wherein

the first gate electrode includes a first metal-containing film formed on the first high dielectric constant insulating film and a first silicon film formed on the first metal-containing film,

the second gate electrode includes a second metal-containing film formed on the second high dielectric constant insulating film and a second silicon film formed on the second metal-containing film,

a silicon dioxide film is interposed between the first silicon film and the first insulating spacers, and

the second silicon film is in contact with the second insulating spacers.

5. The semiconductor device of claim 4 , wherein

a first metal silicide layer is formed on the first silicon film, and

a second metal silicide layer is formed on the second silicon film.

6. The semiconductor device of claim 4 , wherein a silicon dioxide film is also interposed between the first active region and the first sidewall spacers.

7. The semiconductor device of claim 2 , wherein each of the first insulating spacers and the second insulating spacers is made of a silicon nitride film.

8. The semiconductor device of claim 1 , wherein

the first and second MIS transistors are pMIS transistors, and

the first and second high dielectric constant insulating films contain aluminum.

9. The semiconductor device of claim 8 , wherein

the first gate insulating film further includes a first cap film formed on the first high dielectric constant insulating film and containing aluminum, and

the second gate insulating film further includes a second cap film formed on the second high dielectric constant insulating film and containing aluminum.

10. The semiconductor device of claim 1 , wherein

the first and second MIS transistors are nMIS transistors, and

the first and second high dielectric constant insulating films contain lanthanum.

11. The semiconductor device of claim 10 , wherein

the first gate insulating film further includes a first cap film formed on the first high dielectric constant insulating film and containing lanthanum, and

the second gate insulating film further includes a second cap film formed on the second high dielectric constant insulating film and containing lanthanum.

12. The semiconductor device of claim 1 , wherein each of the first and second high dielectric constant insulating films contains hafnium or zirconium.

13. The semiconductor device of claim 1 , wherein the first and second high dielectric constant insulating films are equal in thickness.

14. The semiconductor device of claim 1 , wherein the first and second gate electrodes are made of an identical material.

15. The semiconductor device of claim 1 , wherein an effective work function of the first MIS transistor is higher than an effective work function of the second MIS transistor.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2024
From: NUVOTON TECHNOLOGY CORPORATION JAPAN
To: ADVANCED INTEGRATED CIRCUIT PROCESS LLC
Reel/Frame 068118/0314 →
CHANGE OF NAME Recorded Jun 12, 2024
From: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
To: NUVOTON TECHNOLOGY CORPORATION JAPAN
Reel/Frame 067711/0965 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 053570/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2014
From: ITO, SATORU; MORIYAMA, YOSHIYA; OHKAWA, HIROSHI; AKAMATSU, SUSUMU
To: PANASONIC CORPORATION
Reel/Frame 031968/0651 →