Buffer circuit, scanning circuit, display device, and electronic equipment
View Patent ↗A buffer circuit includes a first transistor circuit having a first conductivity type transistor, a second transistor circuit having a second conductivity type transistors, in which the first and second transistor circuits are serially connected between a first fixed power supply and a second fixed power supply, and input terminals and output terminals of each of the first and second transistor circuits are connected in common respectively, in which at least one transistor circuit of the first transistor circuit and the second transistor circuit is a double gate transistor, and in which wherein a switch element, when any one transistor circuit of the first and the second transistor circuits is in an operating state, is included to supply a voltage of a third fixed power supply to a common connection node of the double gate transistor of the other transistor circuit.
1. A buffer circuit comprising:
a first transistor circuit having a first conductive type transistors;
a second transistor circuit having a second conductive type transistors;
wherein the first and second transistor circuits are serially connected between a first fixed power supply and a second fixed power supply, and input terminals and output terminals of each of the first and second transistor circuits are connected in common respectively,
wherein at least one transistor circuit of the first transistor circuit and the second transistor circuit is a double gate transistor, and
wherein a switch element, when any one transistor circuit of the first and the second transistor circuits is in an operating state, is comprised to supply a voltage of a third fixed power supply to a common connection node of the double gate transistor of the other transistor circuit.
2. The buffer circuit according to claim 1 , wherein a voltage between the first fixed power supply and the third fixed power supply, and a voltage between the third fixed power supply and the second fixed power supply are voltages within a range of a source-drain breakdown voltage of each of the transistors which is included in the first and the second transistor circuits.
3. The buffer circuit according to claim 1 , wherein a voltage of the third fixed power supply is a value between the voltages of the first fixed power supply and the second fixed power supply.
4. The buffer circuit according to claim 3 , wherein a voltage of the third fixed power supply is an average value of the voltages of the first fixed power supply and the second fixed power supply.
5. The buffer circuit according to claim 1 , wherein a voltage of the first fixed power supply is higher than a voltage of a higher voltage side of input voltages applied to the input terminal, and a voltage of the second fixed power supply is lower than a voltage of a lower voltage side of the input voltages.
6. The buffer circuit according to claim 1 , wherein the switch element is a transistor having the same conductive type as the other transistor circuit which forms an inverter circuit.
7. The buffer circuit according to claim 6 , wherein the transistor of the same conductive type has a gate electrode being connected to an output terminal.
8. The buffer circuit according to claim 1 , wherein
the first transistor circuit includes a first and a second P channel transistors of double gate structure which are connected to the input terminal and the gate electrodes thereof being connected in common,
the first P channel transistor has a source electrode being connected to the first fixed power supply,
the second P channel transistor has a drain electrode being connected to the output terminal, and
a drain electrode of the first P channel transistor and a source electrode of the second P channel transistor are connected to each other in common to be the common connection node, and the voltage of the third fixed power supply is supplied to the common connection node by the switch element.
9. The buffer circuit according to claim 1 , wherein
the second transistor circuit includes the first and second N channel transistors of double gate structure which are connected to the input terminal, and the gate electrodes thereof being connected in common,
the first N channel transistor has a drain electrode being connected to the output terminal,
the second N channel transistor has a source electrode being connected to the second fixed power supply,
a source electrode of the first N channel transistor and a drain electrode of the second N channel transistor are connected to each other in common to be the common connection node, and the voltage of the third fixed power supply is supplied to the common connection node by the switch element.
10. The buffer circuit according to claim 1 , wherein the output terminal is connected to an inverter circuit of a final stage.
11. The buffer circuit according to claim 10 , wherein a voltage of the first fixed power supply is higher than a voltage of a positive side power supply of the inverter circuit of the final stage, and a voltage of the second fixed power supply is lower than a voltage of a negative side power supply of the inverter circuit of the final stage.
12. A scanning circuit comprising:
a buffer circuit that outputs a scanning signal to scan pixels disposed in a in a matrix form in an output stage,
wherein the buffer circuit, includes
a first transistor circuit having a first conductive type transistors,
a second transistor circuit having a second conductive type transistors,
wherein the first and second transistor circuits are serially connected between a first fixed power supply and a second fixed power supply, and input terminals and output terminals of each of the first and second transistor circuits are connected in common respectively,
wherein at least one transistor circuit of the first transistor circuit and the second transistor circuit is a double gate transistor, and
wherein a switch element, when any one transistor circuit of the first and the second transistor circuits is in an operating state, is comprised to supply a voltage of a third fixed power supply to a common connection node of the double gate transistor of the other transistor circuit.
13. A display device comprising:
a pixel array section in which pixels each including an electro-optic element are disposed in a in a matrix form, and
a scanning circuit that scans each pixel of the pixel array section and has a buffer circuit in an output stage,
wherein the buffer circuit includes
a first transistor circuit having a first conductive type transistors,
a second transistor circuit having a second conductive type transistors,
wherein the first and second transistor circuits are serially connected between a first fixed power supply and a second fixed power supply, and input terminals and output terminals of each of the first and second transistor circuits are connected in common respectively,
wherein at least one transistor circuit of the first transistor circuit and the second transistor circuit is a double gate transistor, and
wherein a switch element, when any one transistor circuit of the first and the second transistor circuits is in an operating state, is comprised to supply a voltage of a third fixed power supply to a common connection node of the double gate transistor of the other transistor circuit.
14. An electronic equipment having a display device comprising:
a pixel array section in which pixels each including an electro-optic element are disposed in a matrix form, and
a scanning circuit which scans each pixel of the pixel array section and has a buffer circuit in an output stage,
wherein the buffer circuit includes
a first transistor circuit having a first conductive type transistors,
a second transistor circuit having a second conductive type transistors,
wherein the first and second transistor circuits are serially connected between a first fixed power supply and a second fixed power supply, and input terminals and output terminals of each of the first and second transistor circuits are connected in common respectively,
wherein at least one transistor circuit of the first transistor circuit and the second transistor circuit is a double gate transistor, and
wherein a switch element, when any one transistor circuit of the first and the second transistor circuits is in an operating state, is comprised to supply a voltage of a third fixed power supply to a common connection node of the double gate transistor of the other transistor circuit.