IP Library Granted Patent US 8,884,373
Granted Patent B2
US 8,884,373 · App. 13/665,376 · Granted Nov 11, 2014

Semiconductor device

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Quick Facts
Patent No.
US 8,884,373
App. No.
13/665,376
Granted
Nov 11, 2014
Kind
B2
Abstract

A first dual-gate electrode includes a gate electrode located on a first active region and having a first silicon film of a first conductivity type and a gate electrode located on a second active region and having a first silicon film of a second conductivity type. A second dual-gate electrode includes a gate electrode located on a third active region and having a second silicon film of the first conductivity type and a gate electrode located on a fourth active region and having a second silicon film of the second conductivity type. At least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region.

Claims (29)

1. A semiconductor device, comprising:

a first dual-gate electrode; and

a second dual-gate electrode being separated from the first dual-gate electrode, wherein

the first dual-gate electrode includes a first gate electrode located on a first active region and having a first silicon film of a first conductivity type and a second gate electrode located on a second active region and having a first silicon film of a second conductivity type,

the second dual-gate electrode includes a third gate electrode located on a third active region and having a second silicon film of the first conductivity type and a fourth gate electrode located on a fourth active region and having a second silicon film of the second conductivity type,

the first active region and the second active region are isolated from each other with an isolation region interposed therebetween,

the first gate electrode and the second gate electrode are connected to each other on the isolation region, and

at least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region.

2. The semiconductor device of claim 1 , wherein an isolation width between the first active region and the second active region is larger than that between the third active region and the fourth active region.

3. The semiconductor device of claim 1 , wherein at least a portion of the first silicon film of the second conductivity type has a second-conductivity-type impurity concentration substantially equal to that of a portion of the second silicon film of the second conductivity type located on the fourth active region.

4. The semiconductor device of claim 1 , wherein a portion of the first silicon film of the first conductivity type located on the first active region has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region.

5. The semiconductor device of claim 1 , wherein a portion of the first silicon film of the first conductivity type located on the first active region has a first-conductivity-type impurity concentration lower than that of a portion of the first silicon film of the first conductivity type located on the isolation region.

6. The semiconductor device of claim 1 , wherein a portion of the first silicon film of the second conductivity type located on the second active region has a second-conductivity-type impurity concentration lower than that of a portion of the second silicon film of the second conductivity type located on the fourth active region.

7. The semiconductor device of claim 1 , wherein a portion of the first silicon film of the second conductivity type located on the second active region has a second-conductivity-type impurity concentration lower than that of a portion of the first silicon film of the second conductivity type located on the isolation region.

8. The semiconductor device of claim 1 , wherein a portion of the first silicon film of the first conductivity type located on the first active region has a first-conductivity-type impurity concentration substantially equal to that of a portion of the first silicon film of the first conductivity type located on the isolation region.

9. The semiconductor device of claim 1 , wherein a portion of the first silicon film of the first conductivity type located on the isolation region has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region.

10. The semiconductor device of claim 1 , wherein a portion of the first silicon film of the first conductivity type located on the first active region has a first-conductivity-type impurity concentration substantially equal to that of a portion of the second silicon film of the first conductivity type located on the third active region.

11. The semiconductor device of claim 1 , wherein a portion of the first silicon film of the second conductivity type located on the second active region has a second-conductivity-type impurity concentration substantially equal to that of a portion of the second silicon film of the second conductivity type located on the fourth active region.

12. The semiconductor device of claim 1 , wherein

a portion of the first silicon film of the first conductivity type located on the first active region has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region, and

a portion of the first silicon film of the second conductivity type located on the second active region has a second-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the second conductivity type located on the fourth active region.

13. The semiconductor device of claim 1 , wherein

the first gate electrode is a gate electrode of a first PMIS transistor,

the second gate electrode is a gate electrode of a first NMIS transistor,

the third gate electrode is a gate electrode of a second PMIS transistor, and

the fourth gate electrode is a gate electrode of a second NMIS transistor.

14. The semiconductor device of claim 1 , wherein

each of the first gate electrode and the second gate electrode is a gate electrode of a transistor for a logic circuit, and

each of the third gate electrode and the fourth gate electrode is a gate electrode of a transistor for an SRAM circuit.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2024
From: NUVOTON TECHNOLOGY CORPORATION JAPAN
To: ADVANCED INTEGRATED CIRCUIT PROCESS LLC
Reel/Frame 068118/0314 →
CHANGE OF NAME Recorded Jun 12, 2024
From: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
To: NUVOTON TECHNOLOGY CORPORATION JAPAN
Reel/Frame 067711/0965 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2014
From: SATO, YOSHIHIRO; ARAI, HIDEYUKI; YAMADA, TAKAYUKI
To: PANASONIC CORPORATION
Reel/Frame 031968/0653 →