Method and device for high-speed general purpose level-shifting

1. A circuit, comprising:

an alternating current (AC) coupling component configured to receive an input signal from a low voltage domain and output a first voltage signal;

a direct current (DC) biasing component, connected with the AC coupling component, configured to bias the first voltage signal using a bias voltage based on a previous output signal in a high voltage domain; and

a high voltage output amplifier, connected with the DC biasing component, configured to amplify the DC biased voltage signal in the high voltage domain and provide an output signal in the high voltage domain,

wherein the high voltage domain has a greater maximum operating voltage than the low voltage domain,

wherein the AC coupling component comprises: a first capacitor and a second capacitor, and

wherein the DC biasing component comprises: a first resistor connected with the first capacitor; and a second resistor connected with the second capacitor.

2. The circuit of claim 1 , further comprising: a DC bias generation component, connected with the DC biasing component, configured to generate the bias voltage based on the previous output signal.

3. The circuit of claim 2 , wherein the DC bias generation component comprises an invertor configured to receive the output signal in the high voltage domain.

4. The circuit of claim 2 , wherein the DC bias generation component comprises an invertor having a plurality of voltage supplies in the high voltage domain.

5. The circuit of claim 1 , further comprising: a low voltage input amplifier, connected with the AC coupling component, configured to amplify the input signal in the low voltage domain.

6. The circuit of claim 1 , wherein the high voltage output amplifier comprises: a first transistor connected with the first capacitor; and a second transistor connected with the second capacitor.

7. The circuit of claim 2 , wherein the bias generation component further comprises a delay unit to delay the output voltage.

8. The circuit of claim 2 , wherein the high voltage output amplifier comprises a PMOS transistor and an NMOS transistor.

9. A circuit, comprising:

an alternating current (AC) coupling component configured to split an input signal from a low voltage domain into a first voltage signal and a second voltage signal;

a direct current (DC) biasing component configured to bias the first voltage signal with a first varying DC voltage to provide a first DC biased voltage signal and to bias the second voltage signal with a second varying DC voltage to provide a second DC biased voltage signal; and

a high voltage output amplifier, connected with the DC biasing component, configured to amplify the first DC biased voltage signal and the second DC biased voltage signal in a high voltage domain to provide an output signal in the high voltage domain;

wherein the high voltage domain has a greater maximum operating voltage than the low voltage domain.

10. The circuit of claim 9 , further comprising: a first and second DC bias generation components, connected with the DC biasing component, configured to generate the first and second varying DC voltages based on the previous output signal.

11. The circuit of claim 9 , wherein the first and second DC bias generation components respectively comprises a first invertor and a second invertor configured to invert the previous output signal.

12. The circuit of claim 11 , wherein the first invertor has a first plurality of voltage supplies in the high voltage domain and the second invertor has a second plurality of voltage supplies in the low voltage domain.

13. The circuit of claim 9 , further comprising: a low voltage input amplifier, connected with the AC coupling component, configured to amplify the input signal in the low voltage domain.

14. The circuit of claim 9 , wherein the AC coupling component comprises: a first capacitor and a second capacitor.

15. The circuit of claim 14 , wherein the DC biasing component comprises: a first resistor connected with the first capacitor; and a second resistor connected with the second capacitor.

16. The circuit of claim 14 , wherein the high voltage output amplifier comprises: a first transistor connected with the first capacitor; and a second transistor connected with the second capacitor.

17. A circuit, comprising:

an alternating current (AC) coupling component configured to split an input signal into a first voltage signal and a second voltage signal;

a direct current (DC) biasing component configured to bias the first voltage signal with a first DC voltage to provide a first varying DC biased voltage signal and to bias the second voltage signal with a second varying DC voltage to provide a second DC biased voltage signal, the DC biasing component comprising:

a first P-type metal-oxide-semiconductor(PMOS) transistor coupled with a first N-type metal-oxide-semiconductor(NMOS) transistor and being provided with a first predetermined voltage; and

a second PMOS transistor connected with a second NMOS transistor being provided with a second predetermined voltage; wherein the first predetermined voltage is greater than the second predetermined voltage; and

a first voltage output amplifier, connected with the DC biasing component, configured to amplify the first DC biased voltage signal and the second DC biased voltage signal in a first voltage domain to provide an output signal in the first voltage domain.

18. The circuit of claim 17 , further comprising:

a second voltage input amplifier, connected with the AC coupling component, configured to amplify the input signal in the second voltage domain,

wherein the AC coupling component comprises: a first capacitor and a second capacitor.

19. The circuit of claim 18 , wherein:

the first PMOS transistor and the first NMOS transistor are connected with a first resister connected with the first capacitor, and

the second PMOS transistor and the a second NMOS transistor are connected with a second resister connected with the second capacitor.

20. The circuit of claim 17 , wherein the first NMOS transistor is provided with a third predetermined voltage that is less than the second predetermined voltage.