Successive approximation multiplier-divider for signal process and method for signal process
View Patent ↗A multiplier-divider circuit for signal process according to the present invention comprises a digital-to-analog converter, a first counter, a second counter, an oscillation circuit, and a control-logic apparatus. The digital-to-analog converter generates an output signal of the multiplier-divider circuit in accordance with the value of an input signal and a first signal. The first counter generates the first signal in response to a clock signal and the duty cycle of the input signal. The second counter generates a second signal in response to the clock signal and the period of the input signal. The oscillation circuit generates the clock signal in accordance with a third signal. The control-logic apparatus generates the third signal in response to the second signal and a constant. The first signal is correlated to the duty cycle of the input signal. The second signal is correlated to the period of the input signal.
1. A multiplier-divider circuit for signal process, comprising:
a digital-to-analog converter generating an output signal of the multiplier-divider circuit in accordance with the value of an input signal and a first signal;
a first counter generating the first signal in response to a clock signal and the duty cycle of the input signal;
a second counter generating a second signal in response to the clock signal and the period of the input signal;
an oscillation circuit generating the clock signal in accordance with a third signal; and
a control-logic apparatus generating the third signal in response to the second signal and a constant;
wherein the first signal is correlated to the duty cycle of the input signal; the second signal is correlated to the period of the input signal.
2. The circuit as claimed in claim 1 , wherein the constant is related to a full scale value of the first signal.
3. The circuit as claimed in claim 1 , wherein the control-logic apparatus will increase the frequency of the clock signal if the second signal is more than the constant.
4. The circuit as claimed in claim 1 , wherein the frequency of the clock signal is kept If the second signal is equal to the constant.
5. The circuit as claimed in claim 1 , wherein the oscillation circuit comprises a voltage-controlled-oscillator.
6. The circuit as claimed in claim 1 , wherein the output signal of the multiplier-divider circuit is equivalent to the value of the input signal multiplies the duty cycle of the input signal.
7. The circuit as claimed in claim 1 , wherein the output signal of the multiplier-divider circuit is equivalent to the value of the input signal divides the period of the input signal.
8. The circuit as claimed in claim 1 , wherein the first signal, the second signal, and the third signal X are digital signals.
9. A method for signal process, comprising:
generating a first signal in response to a clock signal and the duty cycle of an input signal;
generating an analog output signal in accordance with the value of the input signal and the first signal;
generating a second signal in response to the clock signal and the period of the input signal;
generating a third signal in response to the second signal; and
controlling the clock signal in accordance with the third signal;
wherein the first signal is correlated to the duty cycle of the input signal; the second signal is correlated to the period of the input signal.
10. The method as claimed in claim 9 , further comprising a constant related to a full scale value of the first signal for generating the third signal.
11. The method as claimed in claim 10 , wherein the third signal will be increased to increase the frequency of the clock signal when the second signal is more than the constant.
12. The method as claimed in claim 9 , wherein the analog output signal is equivalent to the value of the input signal multiplies the duty cycle of the input signal.
13. The method as claimed in claim 9 , wherein the analog output signal is equivalent to the value of the input signal divides the period of the input signal.
14. The method as claimed in claim 9 , wherein the input signal is an analog signal.