IP Library Patent Application 13666592
Patent Application
App. No. 13/666,592

POWER FEED ENTRY CIRCUIT FOR TELECOMMUNICATION APPLICATIONS

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Quick Facts
Patent No.
US None
App. No.
13/666,592
Abstract

A power feed entry circuit, a module with the power feed entry circuit, and a daughter board with the power feed entry circuit include a first circuit coupled to inputs and outputs, wherein the first circuit is configured for power connections, return isolation relays, diode Or-ing, and output status-indication light-emitting diodes (LEDs); a second circuit coupled to the first circuit, the inputs, and the outputs, wherein the second circuit is configured with a hot swappable controller and provides common-mode and differential mode power line filtering; a third circuit coupled to the first circuit, wherein the third circuit is configured for alarm monitoring of the first circuit and the second circuit; and a fourth circuit coupled to the first circuit and the third circuit, wherein the fourth circuit comprises a dual feed high and low active field effect transistor Or-ing circuit.

Claims (47)

1 . A power feed entry circuit, comprising:

inputs coupled to redundant power feeds;

outputs coupled to components on a module;

a first circuit coupled to the inputs and the outputs, wherein the first circuit is configured for power connections, return isolation relays, diode Or-ing, and output fuse light emitting diodes (LEDs);

a second circuit coupled to the first circuit, the inputs, and the outputs, wherein the second circuit is configured with a hot swappable controller and for common-mode and differential mode power line filtering;

a third circuit coupled to the first circuit, wherein the third circuit is configured for alarm monitoring of the first circuit and the second circuit; and

a fourth circuit coupled to the first circuit and the third circuit, wherein the fourth circuit comprises a dual feed high and low active field effect transistor Or-ing circuit;

wherein the first circuit, the second circuit, and the fourth comprise high voltage and high current circuits, and wherein the third circuit comprises a high and low voltage and low current circuit.

2 . The power feed entry circuit of claim 1 , wherein the power feed entry circuit is configured for loads in excess of 500 W with a corresponding power dissipation by the first circuit, the second circuit, and the third circuit of less than 2 W.

3 . The power feed entry circuit of claim 1 , wherein the fourth circuit comprises a plurality of Or-ing metal-oxide-semiconductor field-effect transistors (MOSFETs), and wherein the third circuit is configured to monitor voltage drops across the MOSFETs drain-to-source nets for comparison to programmed controller alarm voltage thresholds and for raising alarms based thereon.

4 . The power feed entry circuit of claim 3 , wherein the third circuit is configured to monitor a plurality of components in the first circuit, the second circuit, and the fourth circuit for operational status and for raising alarms based thereon.

5 . The power feed entry circuit of claim 3 , wherein the fourth circuit comprises a failsafe alternate power path using power diodes connected in parallel across each MOSFET.

6 . The power feed entry circuit of claim 5 , wherein the power diodes are arranged in a hybrid parallel diode architecture that provides the capability of supplying power under power path component fault conditions.

7 . The power feed entry circuit of claim 1 , wherein the first circuit comprises an active power feed return current balance to isolate the return current when a feed is removed.

8 . A module for use in high powered telecom applications, comprising:

a board comprising a plurality of connectors to a backplane; and

a power feed entry circuit coupled to some of the plurality of connectors for receiving power feeds and coupled to at least one component on the board for providing isolated power thereto;

wherein the power feed entry circuit comprises:

inputs coupled to the some of the plurality of connectors;

outputs coupled to the at least one component;

a first circuit coupled to the inputs and the outputs, wherein the first circuit is configured for power connections, return isolation relays, diode Or-ing, and output fuse light-emitting diodes (LEDs);

a second circuit coupled to the first circuit, the inputs, and the outputs, wherein the second circuit is configured with a hot-swappable controller and for common-mode and differential mode power line filtering;

a third circuit coupled to the first circuit, wherein the third circuit is configured for alarm monitoring of the first circuit and the second circuit; and

a fourth circuit coupled to the first circuit and the third circuit, wherein the fourth circuit comprises a dual feed high and low active field effect transistor Or-ing circuit;

wherein the first circuit, the second circuit, and the fourth comprise high voltage and high current circuits, and wherein the third circuit comprises a high and low voltage and low current circuit.

9 . The module of claim 8 , wherein the power feed entry circuit is configured for loads in excess of 500 W with a corresponding power dissipation by the first circuit, the second circuit, and the third circuit of less than 2 W.

10 . The module of claim 8 , wherein the fourth circuit comprises a plurality of Or-ing metal-oxide-semiconductor field-effect transistors (MOSFETs), and wherein the third circuit is configured to monitor voltage drops across the MOSFETs drain-to-source nets for comparison to programmed controller alarm voltage thresholds and for raising alarms based thereon.

11 . The module of claim 10 , wherein the third circuit is configured to monitor a plurality of components in the first circuit, the second circuit, and the fourth circuit for operational status and for raising alarms based thereon.

12 . The module of claim 10 , wherein the fourth circuit comprises a failsafe alternate power path using power diodes connected in parallel across each MOSFET.

13 . The module of claim 12 , wherein the power diodes are arranged in a hybrid parallel diode architecture that provides the capability of supplying power under power path component fault conditions.

14 . The module of claim 8 , wherein the first circuit comprises an active power feed return current balance to isolate the return current when a feed is removed.

15 . A daughter board for use in a high powered telecom module, comprising:

a printed circuit board comprising a power feed entry circuit, wherein the printed circuit board is mounted on the high powered telecom module;

wherein the power feed entry circuit comprises:

inputs coupled to a power feed via the module;

outputs coupled to at least one component on the module;

a first circuit coupled to the inputs and the outputs, wherein the first circuit is configured for power connections, return isolation relays, diode Or-ing, and output fuse light emitting diodes (LEDs);

a second circuit coupled to the first circuit, the inputs, and the outputs, wherein the second circuit is configured with a hot-swappable controller and for common-mode and differential mode power line filtering;

a third circuit coupled to the first circuit, wherein the third circuit is configured for alarm monitoring of the first circuit and the second circuit; and

a fourth circuit coupled to the first circuit and the third circuit, wherein the fourth circuit comprises a dual feed high and low active field-effect transistor Or-ing circuit;

wherein the first circuit, the second circuit, and the fourth comprise high voltage and high current circuits, and wherein the third circuit comprises a high and low voltage and low current circuit.

16 . The daughter board of claim 15 , wherein the power feed entry circuit is configured for loads in excess of 500 W with a corresponding power dissipation by the first circuit, the second circuit, and the third circuit of less than 2 W.

17 . The daughter board of claim 15 , wherein the fourth circuit comprises a plurality of Or-ing metal-oxide-semiconductor field-effect transistors (MOSFETs), and wherein the third circuit is configured to monitor voltage drops across the MOSFETs source-to-drain nets for comparison to programmed controller alarm voltage thresholds and for raising alarms based thereon.

18 . The daughter board of claim 17 , wherein the third circuit is configured to monitor a plurality of components in the first circuit, the second circuit, and the fourth circuit for operational status and for raising alarms based thereon.

19 . The daughter board of claim 15 , wherein the fourth circuit comprises a failsafe alternate power path using power diodes connected in parallel across each MOSFET; and

wherein the first circuit comprises an active power feed return current balance to isolate the return current when a feed is removed

20 . The daughter board of claim 19 , wherein the power diodes are arranged in a hybrid parallel diode architecture that provides the capability of supplying power under power path component fault conditions.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2023
From: BANK OF AMERICA, N.A.
To: CIENA CORPORATION
Reel/Frame 065630/0232 →
PATENT SECURITY AGREEMENT Recorded Nov 8, 2019
From: CIENA CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 050969/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 30, 2019
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: CIENA CORPORATION
Reel/Frame 050938/0389 →
PATENT SECURITY AGREEMENT Recorded Jul 16, 2014
From: CIENA CORPORATION
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 033347/0260 →
SECURITY INTEREST Recorded Jul 15, 2014
From: CIENA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 033329/0417 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2012
From: MCGILL, TERRENCE M., SR.; HOBBS, RICHARD M.; WINGROVE, MICHAEL J.
To: CIENA CORPORATION
Reel/Frame 029227/0989 →