IP Library Granted Patent US 10,140,219
Granted Patent B2
US 10,140,219 · App. 13/667,895 · Granted Nov 27, 2018

Multi-port shared cache apparatus

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Quick Facts
Patent No.
US 10,140,219
App. No.
13/667,895
Granted
Nov 27, 2018
Kind
B2
Abstract

An apparatus for use in telecommunications system comprises a cache memory shared by multiple clients and a controller for controlling the shared cache memory. A method of controlling the cache operation in a shared cache memory apparatus is also disclosed. The apparatus comprises a cache memory accessible by a plurality of clients and a controller configured to allocate cache lines of the cache memory to each client according to a line configuration. The line configuration comprises, for each client, a maximum allocation of cache lines that each client is permitted to access. The controller is configured to, in response to a memory request from one of the plurality of clients that has reached its maximum allocation of cache lines, allocate a replacement cache line to the client from cache lines already allocated to the client when no free cache lines in the cache are available.

Claims (46)

1. An apparatus comprising:

a cache memory accessible by a plurality of processes; and

a controller configured to allocate cache lines from a plurality of cache lines of the cache memory to each process of the plurality of processes according to a line configuration, the line configuration identifying for each process of the plurality of processes a maximum number of cache lines that are able to be utilized by the each process irrespective of free cache lines available in the plurality of cache lines, wherein a different maximum number of cache lines are identified for two or more processes of the plurality of processes, wherein each of the plurality of cache lines is able to be allocated to any process of the plurality of processes,

wherein the controller is further configured to

detect a first memory request from at least one process of the plurality of processes;

allocate a cache line from the plurality of cache lines to the at least one process in response to detecting the first memory request, wherein a cache line from the plurality of cache lines is allocated to the at least one process for each memory request from the process until the maximum number of cache lines for the at least one process has been allocated, and wherein each cache line allocated to the at least one process from the plurality of cache lines is not associated with any type of memory request until the cache line is allocated to the at least one process,

detect a second memory request from the at least one process, where the second memory request is detected subsequent to the first request;

determine, in response to the second memory request being detected, that the at least one process has utilized its maximum allocation of cache lines, and

in response to determining that the at least one process has utilized its maximum allocation of cache lines,

determine that a plurality of cache line replacement policies is available;

identify, from a configuration file associated with the at least one process, a cache line replacement policy from the plurality of cache line replacement policies configured for the at least one process, wherein the controller is configured to apply different line replacement policies concurrently to different processes; and

allocate, in accordance with the identified cache line replacement policy, a replacement cache line to the at least one process only from a cache line currently allocated to and already used by the at least one process for a same type of memory request as the detected second memory request, whereby allocating the replacement cache line to the at least one process prevents the at least one process from exceeding its maximum allocation of cache lines irrespective of free cache lines available in the plurality of cache lines.

2. The apparatus of claim 1 , wherein the maximum allocation of cache lines for each process is based on bandwidth.

3. The apparatus of claim 1 , wherein the maximum allocation of cache lines for each process of the plurality of processes is based on a type of access requested by the each process.

4. The apparatus of claim 1 , wherein the controller is configured to maintain a pool of free cache lines that can be accessed by any process that has not utilized its maximum allocation.

5. The apparatus of claim 4 , wherein the controller is configured to selectively add an inactive cache line to the pool if the inactive cache line has been inactive for a configurable period of time.

6. The apparatus of claim 5 , wherein the controller is configured to maintain the inactive cache line if the number of free cache lines in the pool has exceeded a threshold.

7. The apparatus of claim 1 , wherein the controller is configured to select a least recently used cache line from cache lines already allocated to the at least one process as the replacement cache line.

8. The apparatus of claim 1 , wherein the controller is configured to select a least recently used cache line of the cache as a replacement cache line when the at least one process has not utilized its maximum allocation and when no free cache lines are available.

9. A system, comprising:

the apparatus of claim 1 , and

a plurality of processes having shared access to the cache memory of the apparatus.

10. The system of claim 9 , wherein the system is user equipment in a telecommunications system.

11. A method of controlling a cache memory accessible by a plurality of processes, comprising:

accessing at least one line configuration identifying for each process of the plurality of processes a maximum number of cache lines that are able to be utilized by the each process irrespective of free cache lines available in a plurality of cache lines available to each process of the plurality of processes, wherein a different maximum number of cache lines are identified for two or more processes of the plurality of processes, and wherein a cache line is not associated with any type of memory request until the cache line is allocated to a process;

detecting a first memory request from at least one process of the plurality of processes;

allocating a cache line from the plurality of cache lines to the at least one process in response to detecting the first memory request, wherein a cache line from the plurality of cache lines is allocated to the at least one process for each memory request received from the at least one process until the maximum number of cache lines for the at least one process has been allocated, wherein each of the plurality of cache lines is able to be allocated to any process of the plurality of processes, and wherein the cache line is not allocated to the at least one process until requested by the at least one process;

detecting a second memory request from the at least one process, where the second memory request is detected subsequent to the first request;

determining, in response to detecting the second memory request, that all cache lines of the plurality of cache lines have been utilized;

determining, in response to all cache lines of the plurality of cache lines having been utilized, the process has utilized its maximum allocation of cache lines and each cache line in the plurality of cache lines has been utilized; and

in response to determining that all cache lines of the plurality of cache lines have been utilized and the process has utilized its maximum allocation of cache lines,

determining that a plurality of cache line replacement policies is available;

identifying, from a configuration file associated with the at least one process, a cache line replacement policy from the plurality of cache line replacement policies configured for the at least one process, wherein different cache line replacement policies are concurrently applied to two or more different processes of the plurality of processes; and

allocating, in accordance with the identified cache line replacement policy, a replacement cache line to the at least one process only from a cache line currently allocated to and already used by the at least one process for the type of memory request of the detected memory request, whereby allocating the replacement cache line to the at least one process prevents the at least one process from exceeding its maximum allocation of cache lines irrespective of free cache lines available in the plurality of cache lines.

12. The method of claim 11 , comprising configuring the maximum allocation of cache lines for each process of the plurality of processes based on bandwidth.

13. The method of claim 11 , comprising configuring the maximum allocation of cache lines for each process of the plurality of processes based on a type of access request.

14. The method of claim 11 , comprising applying different line replacement policies to different processes.

15. The method of claim 11 , comprising maintaining a pool of free cache lines that can be allocated to any process of the plurality of processes that has not exceeded its maximum allocation.

16. The method of claim 15 , comprising selectively adding a cache line to the pool if the cache line has been inactive for a configurable period of time.

17. The method of claim 11 , comprising selecting a least recently used cache line from cache lines already allocated to the at least one process as the replacement cache line.

18. The method of claim 11 , comprising selecting a least recently used cache line of the cache as a replacement cache line when the at least one process has not utilized its maximum allocation and when no free cache lines are available.

19. A non-transitory computer readable medium having computer executable instructions stored thereon which, when executed, perform the method of claim 11 .

20. The method of claim 11 , further comprising:

maintaining a pool of free cache lines that can be accessed by any process that has not utilized its maximum allocation;

selectively adding an inactive cache line to the pool if the inactive cache line has been inactive for a configurable period of time; and

maintaining the inactive cache line if the number of free cache lines in the pool has exceeded a threshold.

Assignments (5)
NUNC PRO TUNC ASSIGNMENT Recorded Jun 19, 2023
From: BLACKBERRY LIMITED
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 064271/0199 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2023
From: BLACKBERRY LIMITED
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 064104/0103 →
CHANGE OF NAME Recorded Oct 28, 2014
From: RESEARCH IN MOTION LIMITED
To: BLACKBERRY LIMITED
Reel/Frame 034077/0227 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2013
From: DUGGINS, SIMON JOHN
To: RESEARCH IN MOTION UK LIMITED
Reel/Frame 029561/0360 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2012
From: RESEARCH IN MOTION UK LIMITED
To: RESEARCH IN MOTION LIMITED
Reel/Frame 029503/0040 →
Cited By (1)
US 12,639,205