SEMICONDUCTOR DEVICE INCLUDING PLURAL SEMICONDUCTOR CHIPS STACKED TO ONE ANOTHER

1 . A semiconductor device comprising:

an interface chip; and

a plurality of core chips stacked to the interface chip, the core chips having different chip identification information from one another, at least one of the core chips including a penetration electrode that penetrates therethrough, the penetration electrode forming a part of a data signal path that electrically connects the interface chip to the core chips in common, wherein

the interface chip includes a command decoder simultaneously supplying a read command to the core chips, and

each of the core chips includes:

a memory cell array having a plurality of memory cells;

a chip identification information storage unit storing the chip identification information assigned thereto; and

a first output circuit reading a read data from the memory cell array in response to the read command, the first output circuit outputting the read data to the interface chip via the data signal path at a timing corresponding to the chip identification information that is stored in the chip identification information storage unit.

2 . The semiconductor device as claimed in claim 1 , wherein the first output circuits of the core chips output the read data to the data signal path at different timings from one another so as to prevent the read data outputted from different core chips from racing on the data signal path.

3 . The semiconductor device as claimed in claim 1 , wherein

two or more of the core chips include a penetration electrode, respectively,

the data signal path includes a plurality of penetration electrodes electrically connected to one another, and

the plurality of penetration electrodes are vertically aligned.

4 . The semiconductor device as claimed in claim 1 , wherein the first output circuit reads a plurality of read data from the memory cell array in response to the read command, the first output circuit outputting the plurality of read data in serial to the interface chip via the data signal path at the timing corresponding to the chip identification information stored in the chip identification information storage unit.

5 . The semiconductor device as claimed in claim 1 , further comprising a data input/output terminal,

wherein the interface chip includes a second output circuit outputting the read data, which are output from each of the plurality of core chips, to outside through the data input/output terminal.

6 . A semiconductor device comprising:

an interface chip; and

a plurality of core chips stacked to the interface chip, the core chips having different chip identification information from one another, at least one of the core chips including a plurality of penetration electrodes that penetrate therethrough, the penetration electrodes forming a part of a plurality of data signal paths each of which electrically connects the interface chip to the core chips in common, wherein

the interface chip includes a command decoder simultaneously supplying a read command to the core chips, and

each of the core chips includes:

a memory cell array having a plurality of memory cells;

a chip identification information storage unit storing the chip identification information assigned thereto; and

a first output circuit reading a plurality of read data from the memory cell array in response to the read command, the first output circuit outputting the plurality of read data to the interface chip via the data signal paths at a timing corresponding to the chip identification information that is stored in the chip identification information storage unit.

7 . The semiconductor device as claimed in claim 6 , further comprising a data input/output terminal,

wherein the interface chip includes a second output circuit outputting the plurality of read data, which are supplied in parallel via the plurality of data current paths, to outside in serial through the data input/output terminal.

8 . The semiconductor device as claimed in claim 6 , wherein the first output circuits of the core chips output the plurality of read data to the data signal paths at different timings from one another so as to prevent the read data outputted from different core chips from racing on the data signal paths.

9 . The semiconductor device as claimed in claim 6 , wherein

two or more of the core chips include a plurality of penetration electrodes, respectively,

each of the data signal paths includes a plurality of penetration electrodes electrically connected to one another, and

the plurality of penetration electrodes constituting the same data signal path are vertically aligned.

10 . A semiconductor device comprising:

a first semiconductor chip outputting a read command and a clock signal;

a plurality of second semiconductor chips stacked to the first semiconductor chip, each of the second semiconductor chips performing a read operation to read out a data signal stored therein in response to the read command; and

a signal path electrically connected between the first and second semiconductor chips, wherein

each of the second semiconductor chips includes:

a counter circuit performing a count operation in response to the clock signal to generate a count signal; and

an output control circuit outputs the data signal to the signal path when the count signal indicates a predetermined value, and

the predetermined values of the second semiconductor chips are different from one another.

11 . The semiconductor device as claimed in claim 10 , wherein the count signals of the second semiconductor chips indicate the same value as one another.

12 . The semiconductor device as claimed in claim 10 , wherein at least one of the second semiconductor chips is provided with a penetration electrode that penetrate therethrough, the signal path including the penetration electrode.