Circuit layout for thin film transistors in series or parallel
View Patent ↗Multiple thin film transistors are aligned in serial and parallel orientation. A second source region is disposed between a first source region and a first drain region. A second drain region is disposed between the first source region and the first drain region. The second drain region and the second source region substantially coincide. A first gate is disposed between the first source region and the coinciding second source and second drain regions. A second gate region is disposed between the first drain region and the coinciding second source and second drain regions. An semiconductor is disposed between the first source region, the first drain region, and the coinciding second source and second drain regions. A dielectric material is disposed between the semiconductor substrate and the first and second gates.
1. A thin film device, comprising:
a semiconducting material;
a first source region;
a first drain region;
a first gate;
a second gate;
a second source region disposed between the first source region and the first drain region;
a second drain region disposed between the first source region and the first drain region, wherein the second drain region and the second source region coincide, while the first source region and the first drain region remain the first source region and the first drain region regardless of a state of the second source region or the second drain region;
a first channel region disposed between the first source region and the coinciding second source and second drain regions;
a second channel region disposed between the first drain region and the coinciding second source and second drain regions; and
a dielectric material disposed between the semiconductor and the first and second gates.
2. The device of claim 1 , further comprising a plurality of tertiary source regions and a plurality of tertiary drain regions disposed between the first source region and the first drain region, in which at least one of the plurality of tertiary source regions coincides with at least one of the plurality of tertiary drain regions.
3. The device of claim 2 , further comprising a plurality of tertiary gates, at least one of which is disposed between the first source region, the first drain region, and at least one of the plurality of tertiary drain regions that coincides with one of the plurality of tertiary source regions, and in which the dielectric material is disposed between the plurality of tertiary gate regions and the semiconductor film.
4. The device of claim 3 , wherein at least one of the coinciding source and drain regions contains a conductive material.
5. The device of claim 4 , wherein the first drain region and first source region each contain a conductive material.
6. The device of claim 1 , wherein the first drain region and first source region each contain a conductive material.
7. The device of claim 6 , wherein the first gate and second gate are comprised of a conductive material.
8. The device of claim 2 , wherein the plurality of tertiary source regions and the plurality of tertiary drain regions each contain a conductive material.
9. The device of claim 3 , wherein the plurality of tertiary gates is comprised of a conductive material.
10. The device of claim 1 , wherein the semiconducting material is comprised of a solution material.
11. The device of claim 10 , wherein the solution material is comprised of an organic material.