Amplifier circuit
View Patent ↗Class D amplifier circuits for amplifying an input signal. The amplifier has an H-bridge output stage and thus has switches for switchably connecting a first output to a first voltage, e.g. Vdd, or a second voltage (e.g. ground) and for switchably connecting a second output to the first or second voltages. A switch controller is configured to control the H-bridge stage so as to vary between a plurality of states including at least a first state in which the outputs are both connected to the first voltage and a second state in which the outputs are both connected to said second voltage. The switch controller is configured to vary the proportion of time spent in the first state relative to the second state based on an indication of the amplitude of the input signal. The amplifier may therefore have first circuitry for deriving a proportion value (α) based on the input signal (Din) and second circuitry for generating control signals for selecting the first state or said second state based on the proportion value (α).
1. A class D amplifier circuit for amplifying an input signal comprising:
an H-bridge output stage comprising a plurality of switches for switchably connecting a first output to a first voltage or a second voltage and for switchably connecting a second output to said first voltage or said second voltage; and
a switch controller configured to control said plurality of switches so as to vary between a plurality of states comprising at least a first state in which the first and second outputs are both connected to the first voltage and a second state in which said first and second outputs are both connected to said second voltage;
wherein said switch controller is configured to vary the proportion of time spent in the first state relative to the second state based on an indication of the amplitude of the input signal;
wherein the circuit further comprises first circuitry for deriving a proportion value based on said indication of the amplitude of input signal; and
wherein said first circuitry comprises a translation circuit for translating an input signal to a target proportion value.
2. A class D amplifier circuit as claimed in claim 1 wherein said switch controller is configured to reduce disparity between time spent in the first and second states in response to the input signal amplitude increasing and increase disparity between time spent in the first and second states in response to the input signal amplitude decreasing.
3. A class D amplifier circuit as claimed in claim 1 wherein the first voltage is substantially at ground and the second voltage is a supply voltage.
4. A class D amplifier circuit as claimed in claim 1 wherein the switch controller is configured to increase the time spent in the first state compared to the second state in response to the input signal amplitude decreasing.
5. A class D amplifier circuit as claimed in claim 1 wherein the switch controller varies the proportion of time spent in the first state relative to the second state in response to said proportion value.
6. A class D amplifier circuit as claimed in claim 1 wherein said translation circuitry comprises at least one of: a look-up table, a combinatorial logic circuit or a comparator.
7. A class D amplifier circuit as claimed in claim 1 wherein said translation circuitry is configured such that the variation in target proportion value with input signal amplitude includes at least one step-wise change.
8. A class D amplifier circuit as claimed in claim 1 wherein said translation circuitry is configured such that the target proportion value varies continually with variation in input signal amplitude for at least a range of expected signal amplitudes.
9. A class D amplifier circuit as claimed in claim 1 wherein said first circuitry comprises an envelope detector for receiving a version of the input signal and determining the amplitude.
10. A class D amplifier circuit as claimed in claim 1 wherein said first circuitry is configured to vary the proportion value more rapidly in response to increases in amplitude of the input signal than in response to decreases in amplitude of the input signal.
11. A class D amplifier circuit as claimed in claim 10 wherein said first circuitry is configured to apply a delay between a decrease in amplitude of the input signal and any consequent variation in the proportion value.
12. A class D amplifier circuit as claimed in claim 1 comprising second circuitry for generating control signals for selecting said first state or said second state, wherein said second circuitry is responsive to said proportion value.
13. A class D amplifier circuit as claimed in claim 12 comprising a pulse train generation circuit configured to generate, over a set of clock cycles in which the H-bridge output is to be switched to the first state or the second state, a first logic state for a proportion of said set of clock cycles substantially equal to said proportion value and to generate a second logic state for the remainder of said set of clock cycles.
14. A class D amplifier circuit as claimed in claim 13 wherein the pulse train generation circuit comprises a noise shaper circuit.
15. A class D amplifier circuit as claimed in claim 14 wherein the noise shaper circuit comprises a delta-sigma modulator circuit.
16. A class D amplifier circuit as claimed in claim 13 wherein the second circuitry is responsive to the logic state produced by said pulse train generation circuit to select said first state or said second state.
17. A class D amplifier circuit as claimed in claim 12 comprising a quantizer for sampling the input signal and generating an quantizer output which may include zero and wherein said second circuitry is configured to generate said control signals for selecting said first state or said second state in response to a quantizer output of zero.
18. A class D amplifier circuit as claimed in claim 1 wherein the switch controller is configured such that if the indication of the amplitude of the input signal amplitude decreases below a lower threshold the proportion of time that H-bridge stage is switched into the second state for less than a quarter of the time spent in either of the first or second states.
19. A class D amplifier circuit as claimed in claim 1 wherein the switch controller is configured such that if the indication of the amplitude of the input signal amplitude decreases below a lower threshold the H-bridge amplifier stage is not switched into the second state.
20. A class D amplifier circuit as claimed in claim 1 wherein the switch control circuitry is configured such that if the input signal increases above an upper threshold the proportion of time spent in the first state is controlled to be equal to the proportion of time spent in the second state.
21. A class D amplifier circuit as claimed in claim 1 wherein the switch controller is configured such that if the indication of the amplitude of the input signal amplitude decreases below a lower threshold the proportion of time that H-bridge stage is switched into the second state for less than a quarter of the time spent in either of the first or second states, wherein the switch control circuitry is configured such that if the input signal increases above an upper threshold the proportion of time spent in the first state is controlled to be equal to the proportion of time spent in the second state, and wherein said lower threshold is equal to said upper threshold.
22. A class D amplifier circuit as claimed in claim 1 further comprising run length limiter circuitry configured so as to monitor the frequency of switching to the first or second states and to cause the switch controller to introduce an occurrence of switching to either the first or second state as required to maintain at least a desired minimum frequency.
23. A class D amplifier circuit as claimed in claim 17 , further comprising run length limiter circuitry responsive to the quantizer output and acting to modify some quantizer non-zero output samples to be zero.
24. A class D amplifier circuit as claimed in claim 23 wherein the run length limiter circuitry is configured to modify pairs of quantizer non-zero output samples of opposite polarities by replacing with pairs of zero outputs.
25. A class D amplifier circuit as claimed in claim 23 wherein the run length limiter circuitry is configured to replace a quantizer non-zero output indicating one polarity followed by a non-zero output indicating the opposite polarity with two outputs of zero.
26. A class D amplifier circuit as claimed in claim 23 wherein the run length limiter circuitry is responsive to the quantizer output and acts to modify a quantizer non-zero output to be zero as required to maintain at least a desired minimum frequency of zero outputs.
27. A class D amplifier circuit as claimed in claim 1 comprises edge-filter circuitry configured to receive a signal indicating the desired states of the H-bridge stage and to re-order the occurrence of the states if required in order to reduce the number of state transitions.
28. A class D amplifier circuit as claimed in claim 1 comprising a feedback path from the outputs of the output stage configured to provide a feedback signal to be compared to the input signal.
29. An integrated circuit comprising a class D amplifier circuit as claimed in claim 1 .
30. A driver circuit comprising a class D amplifier circuit as claimed in claim 1 .
31. A driver circuit as claimed in claim 30 wherein said driver circuit is arranged to drive at least one of: an audio transducer, a haptic transducer, an ultrasound transducer; or an electromechanical actuator or motor.
32. An electronic device comprising a circuit as claimed in claim 1 .
33. An electronic device as claimed in claim 32 wherein the device is at least one of: a portable device; a battery powered device; a mobile communications device; a computing device; a gaming device; an audio device; or an ultrasonic device.
34. A method of amplifying an input signal in a Class-D amplifier having an H-bridge stage comprising:
switchably connecting a first output between a first and a second voltage and switchably connecting a second output between the first and the second voltage so as to amplify the input signal; and
varying the proportion of time spent in a first state in which the first and second outputs are both connected to the first voltage relative to a second state in which said first and second outputs are both connected to said second voltage based on an indication of the amplitude of the input signal
wherein the method comprises deriving a proportion value based on said indication of the amplitude of the input signal by using a translation circuit to translate an input signal to a target proportion value.
35. A method as claimed in claim 34 comprising reducing disparity between time spent in the first and second states in response to the input signal amplitude increasing and increasing disparity between time spent in the first and second states in response to the input signal amplitude decreasing.
36. A method as claimed in claim 34 comprising increasing the time spent in the first state compared to the second state in response to the input signal amplitude decreasing.
37. A method as claimed in claim 34 comprising varying the proportion of time spent in the first state relative to the second state in response to said proportion value.
38. A class D amplifier circuit for amplifying an input signal comprising:
an H-bridge output stage comprising first and second outputs;
a switch controller configured to control said H-bridge output stage so as to vary between a plurality of states comprising at least a first state in which the first and second outputs are both connected to a first voltage and a second state in which said first and second outputs are both connected to a second voltage;
wherein said switch controller comprises translation circuit for translating an input signal to a target proportion value based on an indication of the amplitude of the input signal so as to vary the proportion of time spent in the first state relative to the second state.