IP Library Granted Patent US 8,754,534
Granted Patent B2
US 8,754,534 · App. 13/673,990 · Granted Jun 17, 2014

Semiconductor device

Inventors: Minoru Shinohara (Tokyo, JP); Makoto Araki (Tokyo, JP); Michiaki Sugiyama (Tokyo, JP)
Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,754,534
App. No.
13/673,990
Granted
Jun 17, 2014
Kind
B2
Abstract

A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.

Claims (14)

1. A semiconductor device in which a plurality of memory chips are mounted in a stacked manner on a main surface of a wiring board, wherein:

the plurality of memory chips includes at least four memory chips,

each of the plurality of memory chips has a front main surface facing away from the wiring board and a rear main surface opposite the front main surface and facing toward the wiring board,

the front main surface of each of the plurality of memory chips has a respective first side,

respective first terminals are formed on the first side of the front main surface of each of the plurality of memory chips,

the plurality of memory chips are stacked in a dislocated manner along a direction perpendicular to the first side of each front main surface so that the first terminals provided on the first side of each front main surface are exposed from other memory chips of the plurality,

the first side of a memory chip of a lowermost layer of the plurality of memory chips is disposed in line with a first side of the wiring board,

a number of the memory chips dislocated continuously in a same direction is at least two,

except for a memory chip of an uppermost layer in the plurality of memory chips, a memory chip of an uppermost layer in a group of the memory chips dislocated continuously in the same direction is stacked in a state of being rotated 180° degrees from each other memory chip in the group,

an interposer is provided on the memory chip of the uppermost layer of the plurality of memory chips,

the interposer is connected to a memory chip having the first terminals thereof disposed toward the first side of the wiring board or a memory chip having second terminals on a side opposite to the first side of the wiring board through first wires,

the interposer is further connected to the wiring board through second wires,

a memory controller chip for controlling the memory chips is provided on the interposer, and

the memory controller chip is electrically connected to the interposer.

Assignments (1)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
Priority Claims (2)
JP 2008-029691 · Feb 8, 2008 · national
JP 2008-198535 · Jul 31, 2008 · national
Continuity (3)
Division 13158430 · Jun 12, 2011
Division 12365806 · Feb 4, 2009
Related Publication 20130069249A1 · Mar 21, 2013