IP Library Granted Patent US 9,190,959
Granted Patent B2
US 9,190,959 · App. 13/674,599 · Granted Nov 17, 2015

Circuit, transceiver and mobile communication device

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Quick Facts
Patent No.
US 9,190,959
App. No.
13/674,599
Granted
Nov 17, 2015
Kind
B2
Abstract

A circuit for providing a bias signal for a power amplifier includes a first input, a second input and an output. The first input is configured to receive an input signal to be amplified by the power amplifier. The second input is configured to receive the amplified input signal. The output is configured to provide the bias signal.

Claims (24)

1. A circuit for providing a bias signal for a power amplifier, the circuit comprising:

a first input configured to receive an input signal comprising a digital baseband signal to be amplified by the power amplifier,

a second input configured to receive the amplified input signal,

an output configured to provide the bias signal;

a bias modifier configured to vary the bias signal for the power amplifier based on the input signal, wherein the bias modifier comprises a mapper configured to map the amplitude of the digital baseband signal to a digital voltage signal based on a predetermined relationship and a digital-to-analog converter (DAC) configured to convert the mapped digital voltage signal into the bias signal for the power amplifier;

a feedback receiver configured to determine an information describing the amplified input signal; and

an adjuster configured to adjust a distortion compensation rule based on the information describing the amplified input signal, which is provided by the feedback receiver, to counteract or compensate a distortion of the amplified input signal.

2. The circuit according to claim 1 , wherein the adjuster is configured to adjust the distortion compensation rule to counteract or compensate a distortion of the amplified input signal induced by the bias signal variation.

3. The circuit according to claim 1 ,

wherein the bias modifier is configured to perform an envelope tracking (ET) modulation,

wherein the feedback receiver and the adjuster are configured to perform an amplitude modulation (AM), and

wherein the adjuster is configured to adjust the distortion compensation rule to counteract or compensate a distortion of the amplified input signal induced by a time misalignment between the amplitude modulation (AM) and the envelope tracking (ET) modulation.

4. The circuit according to claim 1 , further comprising:

a predistorter configured to perform a predistortion of the input signal to obtain a predistorted signal for the power amplifier,

wherein the adjuster is configured to adjust a predistortion rule, and

wherein the predistorter is configured to apply the predistortion rule to obtain the predistorted signal for the power amplifier.

5. The circuit according to claim 1 , wherein the feedback receiver is configured to determine an amplitude information (A) and/or a phase information (φ) as the information describing the amplified input signal.

6. The circuit according to claim 1 , wherein the feedback receiver is configured to determine the information describing the amplified input signal using a measurement signal provided by a detector.

7. The circuit according to claim 1 ,

wherein the adjuster comprises a calculator configured to calculate correction values from the information describing the amplified input signal,

wherein the adjuster is configured to adjust the distortion compensation rule using the calculated correction values.

8. The circuit according to claim 7 ,

wherein the feedback receiver is configured to determine an amplitude information (A) and/or a phase information (φ) describing the amplified input signal, and

wherein the calculator is configured to compare the amplitude information (A) and/or the phase information (φ) describing the amplified input signal and the amplitude information and/or the phase information describing a desired input signal and calculate the correction values on the basis of the amplitude information and/or the phase information comparison.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2012
From: CAMUFFO, ANDREA; BELITZER, ALEXANDER; SOGL, BERNHARD
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 029541/0267 →