Generation of multilevel signals using correlative coding
View Patent ↗Disclosed is a polybinary-signal generator in which correlative coding is applied to a plurality of fractional-bit-rate signals instead of being applied to a corresponding multiplexed full-bit-rate signal. The resulting coded fractional-bit-rate signals are variously delayed with respect to one another and then summed to generate a polybinary output signal. One beneficial feature of this architecture is that most circuit components of the polybinary-signal generator operate at the fractional bit rate, which helps to alleviate at least some of the technical difficulties associated with the design of radio-frequency circuits intended for relatively high bit rates. Another beneficial feature of this architecture is that the polybinary-signal generator also serves as a signal multiplexer.
1. An apparatus comprising:
a coder circuit having a plurality of input ports and a plurality of output ports and configured to:
receive a plurality of binary input streams, with each being received at a respective one of the plurality of input ports;
generate a plurality of coded binary streams, with each of said coded binary streams being generated from a respective set of binary input streams from the plurality of binary input streams and a respective set of other coded binary streams from the plurality of coded binary streams; and
apply each of the plurality of coded binary streams to a respective one of the plurality of output ports;
a set of delay elements, each coupled to a respective one of the plurality of output ports of the coder circuit and configured to apply a respective time delay to a respective one of the coded binary streams; and
an adder circuit configured to sum delayed coded binary streams received from the set of delay elements to generate a multilevel signal having N+1 signal levels, where N is a positive integer greater than two; and
wherein the apparatus is configured to operate such that:
each of the binary input streams has a bit rate of 1/NT, where NT is a bit duration in the binary input streams; and
the multilevel signal has a bit rate of 1/T.
2. The apparatus of claim 1 , wherein:
the plurality of binary input streams comprises N binary input streams;
the plurality of coded binary streams comprises N coded binary streams;
the respective set of binary input streams comprises a respective one of the N binary input streams; and
the respective set of other coded binary streams comprises respective N−1 of the N coded binary streams.
3. The apparatus of claim 1 , wherein:
each delay element from the set of delay elements is configured to apply a time delay that is different from a time delay applied by any other delay element from the set of delay elements; and
any two delay elements in the set of delay elements have time delays that differ from one another by a value that is smaller than a bit duration in the coded binary streams.
4. The apparatus of claim 1 , further comprising a de-multiplexer configured to generate the plurality of binary input streams by de-multiplexing a binary data stream having a higher bit rate than any of the plurality of the binary input streams.
5. The apparatus of claim 1 , wherein the coder circuit is configured to mix the respective sets using a type of correlative coding that causes the multilevel signal to be a polybinary signal.
6. The apparatus of claim 1 , wherein the apparatus is further configured to operate so that each of the coded binary streams has the bit rate of 1/NT.
7. The apparatus of claim 1 , wherein each of the plurality of input ports and the plurality of output ports has N ports.
8. The apparatus of claim 7 , wherein N is smaller than 129.
9. The apparatus of claim 7 , wherein N=3.
10. The apparatus of claim 9 , wherein the coder circuit is configured to generate a first coded binary stream, y 1 [k], a second coded binary stream, y 2 [k], and a third coded binary stream, y 3 [k], of the plurality of coded binary streams in accordance with the following equations:
y 1 [k]=y 3 [k− 1] y 2 [k− 1] x 1 [k];
y 2 [k]=y 1 [k]y 3 [k− 1] x 2 [k];
y 3 [k]=y 2 [k]y 1 [k]x 3 [k],
where k is a time-slot index; x 1 [k] is a first of the plurality of binary input streams; x 2 [k] is a second of the plurality of binary input streams; and x 3 [k] is a third of the plurality of binary input streams.
11. The apparatus of claim 7 , wherein N=4.
12. The apparatus of claim 11 , wherein the coder circuit is configured to generate a first coded binary stream, y 1 [k], a second coded binary stream, y 2 [k], a third coded binary stream, y 3 [k], and a fourth coded binary stream, y 4 [k], of the plurality of coded binary streams in accordance with the following equations:
y 1 [k]=y 4 [k− 1] y 3 [k− 1] y 2 [k− 1] x 1 [k];
y 2 [k]=y 1 [k]y 4 [k− 1] y 3 [k− 1] x 2 [k];
y 3 [k]=y 2 [k]y 1 [k]y 4 [k− 1] x 3 [k];
y 4 [k]=y 3 [k]y 2 [k]y 1 [k]x 4 [k],
where k is a time-slot index; x 1 [k] is a first of the plurality of binary input streams; x 2 [k] is a second of the plurality of binary input streams; x 3 [k] is a third of the plurality of binary input streams; and x 4 [k] is a fourth of the plurality of binary input streams.
13. The apparatus of claim 7 , wherein the set of delay elements comprises N delay elements, each having a different relative time delay selected from a set of values consisting of 0, T, 2T, . . . , [N−1] T, where NT is a bit duration in the binary input streams.
14. The apparatus of claim 7 , wherein:
the coder circuit comprises:
N XOR gates, each having N input terminals and an output terminal; and
N−1 flip-flops; and
for each of the N XOR gates,
the output terminal is connected to a respective one of the N output ports of the coder circuit;
one of the N input terminals is connected to a respective one of the N input ports of the coder circuit; and
each of other N−1 input terminals of the N input terminals is connected, either directly or through a respective one of the N−1 flip-flops, to a respective one of other N−1 output ports of the coder circuit.
15. The apparatus of claim 14 , wherein each of the N XOR gates has a different respective number of said other N−1 input terminals connected directly to the output ports, with said different respective numbers selected from a set consisting of 0, 1, 2, . . . , N−1.
16. The apparatus of claim 14 , wherein the flip-flops are controlled by a clock signal having a rate of 1/NT, where NT is a bit duration in the binary input streams.
17. An apparatus comprising a coder circuit having N input ports and N output ports, where N is a positive integer greater than two, wherein:
the coder circuit comprises:
N XOR gates, each having N input terminals and an output terminal; and
N−1 flip-flops; and
for each of the N XOR gates,
the output terminal is connected to a respective one of the N output ports of the coder circuit;
one of the N input terminals is connected to a respective one of the N input ports of the coder circuit; and
each of other N−1 input terminals of the N input terminals is connected, either directly or through a respective one of the N−1 flip-flops, to a respective one of other N−1 output ports of the coder circuit.
18. The apparatus of claim 17 , wherein each of the N XOR gates has a respective number of said other N−1 input terminals connected directly to the output ports, with said respective numbers selected from a set consisting of 0, 1, 2, . . . , N−1.
19. The apparatus of claim 17 , wherein the flip-flops are controlled by a clock signal having a rate of 1/NT, where NT is a bit duration in the binary input streams.
20. An apparatus comprising:
a coder circuit having a plurality of input ports and a plurality of output ports and configured to:
receive a plurality of binary input streams, with each being received at a respective one of the plurality of input ports;
generate a plurality of coded binary streams, with each of said coded binary streams being generated from a respective set of binary input streams from the plurality of binary input streams and a respective set of other coded binary streams from the plurality of coded binary streams; and
apply each of the plurality of coded binary streams to a respective one of the plurality of output ports;
a set of delay elements, each coupled to a respective one of the plurality of output ports of the coder circuit and configured to apply a respective time delay to a respective one of the coded binary streams; and
an adder circuit configured to sum delayed coded binary streams received from the set of delay elements to generate a multilevel signal having N+1 signal levels, where N is a positive integer greater than two, wherein:
each delay element from the set of delay elements is configured to apply a time delay that is different from a time delay applied by any other delay element from the set of delay elements; and
any two delay elements in the set of delay elements have time delays that differ from one another by a value that is smaller than a bit duration in the coded binary streams.
21. An apparatus comprising:
a coder circuit having a plurality of input ports and a plurality of output ports and configured to:
receive a plurality of binary input streams, with each being received at a respective one of the plurality of input ports;
generate a plurality of coded binary streams, with each of said coded binary streams being generated from a respective set of binary input streams from the plurality of binary input streams and a respective set of other coded binary streams from the plurality of coded binary streams; and
apply each of the plurality of coded binary streams to a respective one of the plurality of output ports;
a set of delay elements, each coupled to a respective one of the plurality of output ports of the coder circuit and configured to apply a respective time delay to a respective one of the coded binary streams; and
an adder circuit configured to sum delayed coded binary streams received from the set of delay elements to generate a multilevel signal having N+1 signal levels, where N is a positive integer greater than two; and
wherein the coder circuit is configured to mix the respective sets using a type of correlative coding that causes the multilevel signal to be a polybinary signal.