Semiconductor device
Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.
1. A semiconductor device, comprising:
(a1) a first transistor coupled between a first potential and a first node;
(a2) a second transistor coupled between the first node and a second potential lower than the first potential;
(a3) a third transistor coupled between the first potential and a second node;
(a4) a fourth transistor coupled between the second node and the second potential;
(a5) a fifth transistor coupled between the first node and a first bit line;
(a6) a sixth transistor coupled between the second node and a second bit line;
(b1) a first active region which is surrounded by an isolation region and in which the fifth transistor is disposed;
(b2) a second active region which is surrounded by the isolation region and in which the sixth transistor is disposed;
(c) an insulating layer disposed under the first active region and the second active region;
(d1) a first semiconductor region of a first conductivity type disposed under the first active region via the insulating layer; and
(d2) a second semiconductor region of a second conductivity type opposite to the first conductivity type disposed under the first semiconductor region,
wherein a bottom portion and a side portion of the first semiconductor region are disposed so as to come in contact with the second semiconductor region, and
wherein the first semiconductor region is coupled to a gate electrode of the fifth transistor.
2. A semiconductor device according to claim 1 , further comprising:
(d3) a third semiconductor region of the first conductivity type disposed under the second active region via the insulating layer,
wherein a bottom portion and a side portion of the third semiconductor region are disposed so as to come in contact with the second semiconductor region, and
wherein the third semiconductor region is coupled to a gate electrode of the sixth transistor.
3. A semiconductor device according to claim 2 , further comprising:
(b3) a third active region which is surrounded by the isolation region and in which the first transistor is disposed,
wherein, under the third active region, the second semiconductor region is disposed via the insulating layer.
4. A semiconductor device according to claim 3 ,
wherein the first, second, and third active regions are arranged to be aligned in a first direction,
wherein the third active region is disposed between the first active region and the second active region, and
wherein the second semiconductor region disposed under the third active region via the insulating layer extends to positions under the first semiconductor region and the third semiconductor region.
5. A semiconductor device according to claim 4 , further comprising:
(b4) a fourth active region which is surrounded by the isolation region and in which the second transistor is disposed,
wherein the fourth active region is disposed between the third active region and the second active region.
6. A semiconductor device according to claim 5 ,
wherein the third transistor is disposed in the first active region, and the fourth transistor is disposed in the second active region.
7. A semiconductor device according to claim 1 ,
wherein the coupling between the first semiconductor region and the gate electrode of the fifth transistor is achieved by an indiscrete first conductive film extending from over the gate electrode of the fifth transistor to over the first semiconductor region.
8. A semiconductor device according to claim 2 ,
wherein the coupling between the second semiconductor region and the gate electrode of the sixth transistor is achieved by an indiscrete second conductive film extending from over the gate electrode of the sixth transistor to over the second semiconductor region.
9. A semiconductor device according to claim 1 , further comprising:
a memory cell array including a plurality of memory cells each including the first to six transistors, the memory cells being repeatedly arranged line-symmetrically with respect to a line extending in a first direction and line-symmetrically with respect to a line extending in a second direction intersecting the first direction,
wherein, in the memory cell array, a plurality of the first semiconductor regions are arranged with a first spacing being provided therebetween in the first direction and with a second spacing being provided therebetween in the second direction, and
wherein the second semiconductor region is disposed to come in contact with the bottom portion and the side portion of each of the first semiconductor regions and continuously disposed so as to be located under the insulating layer in a first portion in which the first spacing is provided and in a second portion in which the second spacing is provided.
10. A semiconductor device according to claim 1 , wherein the first conductivity type is a p-type and the second conductivity type is an n-type.
11. A semiconductor device according to claim 1 , wherein the first conductivity type is an n-type and the second conductivity type is a p-type.
12. A semiconductor device according to claim 11 , wherein the gate electrode of the fifth transistor has a metal portion.
13. A semiconductor device according to claim 12 , wherein a gate insulating film located between the gate electrode of the fifth transistor and the first active region has an insulating film portion having a dielectric constant higher than that of a silicon oxide film.
14. A semiconductor device according to claim 7 , wherein the first conductive film achieving the coupling between the first semiconductor region and the gate electrode of the fifth transistor is disposed to extend through the isolation region.
15. A semiconductor device according to claim 14 , wherein the first conductive film is disposed in the isolation region and in an interlayer insulating film disposed over the isolation region.
16. A semiconductor device according to claim 15 , further comprising:
a third conductive film disposed over each of source/drain regions of the fifth transistor,
wherein a first coupling hole in which the first conductive film is disposed is formed by a step different from a step by which a second coupling hole in which the third conductive film is disposed is formed.
17. A semiconductor device according to claim 7 ,
wherein the first conductive film achieving the coupling between the first semiconductor region and the gate electrode of the fifth transistor is not disposed to extend through the isolation region, and
wherein a bottom portion of the first conductive film is coupled to the first semiconductor region at a position higher than that of a bottom portion of the isolation region.
18. A semiconductor device according to claim 17 ,
wherein the first conductive film is made of a conductive material formed in a coupling hole, and
wherein the coupling hole is formed in an opening region including a region in which the first conductive film is formed after the insulating layer located in the opening region and a semiconductor region over the insulating layer are removed.
19. A semiconductor device according to claim 18 , further comprising:
a third conductive film disposed over each of source/drain regions of the fifth transistor,
wherein a first coupling hole in which the first conductive film is disposed is formed by the same step as that by which a second coupling hole in which the third conductive film is disposed is formed.