Input buffer circuit of semiconductor apparatus

1. An input buffer circuit of a semiconductor apparatus, comprising:

a bias voltage level control unit configured to output a control bias voltage by decreasing a bias voltage, when a level of the bias voltage becomes higher than a target level;

a first buffering unit configured to generate a compare signal by comparing a voltage level of an input signal with a level of a reference voltage, when being activated by receiving the control bias voltage; and

a second buffering unit configured to generate an output signal by comparing the voltage levels of the input signal and the compare signal.

2. The input buffer circuit of a semiconductor apparatus according to claim 1 , wherein the bias voltage level control unit outputs the bias voltage as the control bias voltage, when the bias voltage level is lower than the target voltage level.

3. The input buffer circuit of a semiconductor apparatus according to claim 2 , wherein the bias voltage level control unit includes:

a level detector configured to generate a detection signal by detecting the bias voltage level;

a voltage dropper configured to generate a down voltage by decreasing the bias voltage; and

a selector configured to selectively output the bias voltage or the down voltage as the control bias voltage, in response to the detection signal.

4. The input buffer circuit of a semiconductor apparatus according to claim 3 , wherein the level detector enables the detection signal, when the bias voltage level is higher than the target voltage level, and

disables the detection signal, when the bias voltage level is lower than the target voltage level.

5. The input buffer circuit of a semiconductor apparatus according to claim 4 , wherein the selector outputs the down voltage as the control bias voltage, when the detection signal is enabled, and

outputs the bias voltage as the control bias voltage, when the detection signal is disabled.

6. An input buffer circuit of a semiconductor apparatus, comprising:

a first buffering unit configured to include a voltage dropper decreasing voltage levels of a first compare signal and a second compare signal in response to voltage levels of reference voltage and an input signal, and a voltage applier increasing the voltage levels of the first and second compare signals in response to the voltage levels of the reference voltage and the second compare signal; and

a second buffering unit configured to generate an output signal by comparing the voltage levels of the first compare signal and the input signal.

7. The input buffer circuit of a semiconductor apparatus according to claim 6 , wherein the voltage dropper decreases the voltage level of the first compare signal less than the voltage level of the second compare signal, when the voltage level of the input signal is higher than the level of the reference voltage, and

decreases the voltage level of the second compare signal less than the voltage level of the first compare signal, when the voltage level of the input signal is lower than the reference voltage level.

8. The input buffer circuit of a semiconductor apparatus according to claim 6 , wherein the voltage applier increases the voltage level of the first and second compare signal more than when the voltage level of the second compare signal is higher than the reference voltage level, when the voltage level of the second compare signal is lower than the level of the reference voltage.

9. The input buffer circuit of a semiconductor apparatus according to claim 8 , wherein the voltage applier includes: a comparator that generates a control signal by comparing the second compare signal with the level of the reference voltage; and a variable resistor having a resistance level that changes in response to a voltage level of the control signal, and

the variable resistor is configured to increase the voltage level of the first and second compare signals by receiving external voltage.