IP Library Granted Patent US 8,999,831
Granted Patent B2
US 8,999,831 · App. 13/680,257 · Granted Apr 7, 2015

Method to improve reliability of replacement gate device

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Quick Facts
Patent No.
US 8,999,831
App. No.
13/680,257
Filed
Nov 19, 2012
Granted
Apr 7, 2015
Kind
B2
Art Unit
2899
USPC
438/478
Abstract

A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; annealing the structure at a high temperature of not less than 800° C.; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. Optionally, a second annealing step can be performed after the first anneal. This second anneal is performed as a millisecond anneal using a flash lamp or a laser.

Claims (16)

1. A method of fabricating a gate stack for a semiconductor device, said method comprising steps of:

after removal of a dummy gate, providing a replacement gate structure by performing steps of:

growing a high-k dielectric layer over an area vacated by the dummy gate;

depositing a thin metal layer over the high-k dielectric layer;

depositing a sacrificial layer over the thin metal layer;

performing a first rapid thermal anneal of the replacement gate structure at a high temperature of not less than 800° C.;

removing both the thin metal layer and the sacrificial layer;

performing a second rapid thermal anneal at a temperature range between 400° C. and 800° C., inclusive;

re-depositing a thin metal layer over the high-k dielectric layer after performing the second rapid thermal anneal; and

depositing a second metal layer.

2. The method of claim 1 wherein performing the first and second rapid thermal anneals comprises annealing the structure in ambient nitrogen.

3. The method of claim 1 wherein depositing the sacrificial layer comprises depositing a layer of polycrystalline silicon.

4. The method of claim 1 wherein depositing the sacrificial layer comprises depositing a layer of amorphous silicon.

5. The method of claim 1 wherein depositing the second metal layer comprises:

depositing a work function metal; and

depositing a gap fill metal of low resistivity.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2012
From: ANDO, TAKASHI; CARTIER, EDUARD A.; CHOI, KISIK; NARAYANAN, VIJAY
To: INTERNATIONAL BUSINESS MACHINES CORPORATION; GLOBALFOUNDRIES, INC.
Reel/Frame 029319/0178 →