IP Library Granted Patent US 8,949,478
Granted Patent B2
US 8,949,478 · App. 13/680,539 · Granted Feb 3, 2015

Intelligent serial interface

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,949,478
App. No.
13/680,539
Granted
Feb 3, 2015
Kind
B2
Abstract

An intelligent serial interface circuit in accordance with one embodiment of the invention can include a first communication interface circuit for enabling a first communication protocol. The intelligent serial interface circuit can also include a second communication interface circuit for enabling a second communication protocol. Furthermore, the intelligent serial interface circuit can include a detector circuit coupled to the first communication interface circuit and the second communication interface circuit. The detector circuit can be for automatically detecting a factor that indicates automatically enabling the first communication interface circuit and automatically disabling the second communication interface circuit. The detector circuit can be for detecting a coupling of a pin of the first communication interface circuit that is not used by the second communication interface circuit.

Claims (8)

1. A method comprising:

driving an output pin of an integrated circuit that comprises a first communication interface and a second communication interface;

determining if a state of the output pin is similar to a predefined state;

if the state of the output pin is similar to the predefined state, automatically enabling the first communication interface and disabling the second communication interface; and

if the state of the output pin is not similar to the predefined state, automatically enabling the second communication interface and disabling the first communication interface.

2. The method of claim 1 , wherein the first communication interface comprises a Serial Peripheral Interface (SPI) bus slave interface.

3. The method of claim 1 , wherein the second communication interface comprises an Inter-Integrated Circuit (I 2 C) bus slave interface.

4. The method of claim 1 , wherein the predefined state comprises a voltage level.

Assignments (6)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2013
From: WRIGHT, DAVID G.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 030329/0310 →