Systems and methods for digital interface translation
View Patent ↗Systems and methods of digital interface translation are described. One embodiment of the invention includes multiple receiver lanes, where at least one of the receiver lanes is configured to receive a data channel at a first data rate and encoded in accordance with an input digital interface standard, an auxiliary channel input configured to receive an auxiliary data channel, and a single transmitter lane configured to output a single data channel at a second data rate and encoded in accordance with an output digital interface standard. In addition, the multilane to single lane digital interface translator is configured to decode the received data into data streams, and interleave the data streams to form packets, the multilane to single lane digital interface translator is configured to insert auxiliary data received via the auxiliary channel input and idle data between the packets to produce an output data stream that is rate matched to the second data rate, and the multilane to single lane digital interface translator is configured to encode the output data stream in accordance with the output digital interface standard.
1. A single lane to multilane digital interface translator, comprising:
a single receiver lane configured to receive a single input data channel at a first data rate encoded in accordance with an input digital interface standard, where the input data channel includes packets, and auxiliary data and idle data inserted between the packets, and where each packet contains encoded code groups, where the encoded code groups are encoded in accordance with the input digital interface standard and all of the encoded code groups in each packet are of the same type;
multiple transmitter lanes, where at least one of the transmitter lanes is configured to transmit an output data channel encoded in accordance with an output digital interface standard; and
an auxiliary channel output configured to transmit an auxiliary data channel;
wherein the single lane to multilane digital interface translator is configured to extract auxiliary data inserted between received packets and output the auxiliary data via the auxiliary channel;
wherein the single lane to multilane digital interface translator is configured to decode the data within the packets received on the single receiver lane to produce the encoded code groups;
wherein the single lane to multilane digital interface translator is configured to deinterleave the encoded code groups and discarding the idle data so that deinterleaved encoded code groups of the same type are on each of the transmitter lanes at any given time and to decode the deinterleaved encoded code groups to obtain at least one output stream at a second data rate; and
wherein the single lane to multilane digital interface translator is configured to encode the deinterleaved decoded code groups according to the type of the code group and encode the at least one output stream in accordance with the output digital interface standard.
2. The digital interface translator of claim 1 , wherein the multiple transmitter lanes are configurable to encode the decoded code groups for output on at least one data channel in accordance with one of a plurality of digital interface standards.
3. The digital interface translator of claim 1 , wherein the input digital interface standard is the 10 Gigabit IEEE 802.3 Clause 49 standard.
4. The digital interface translator of claim 1 , wherein the output digital interface standard is the Display Port standard.
5. The digital interface translator of claim 4 , wherein the digital interface translator is configured to utilize the following definitions:
∥C∥=/K 0 x.y/K 1 x.y/K 2 x.y/K 3 x.y/
∥D∥=/D 0 x.y/D 1 x.y/D 2 x.y/D 3 x.y/
∥S dp ∥=/S/D0.0/D0.0/D0.0/
∥T 0 ∥=/T/I/I/I/, defined in IEEE 802.3 Clause 48
∥I∥=/I/I/I/I/, defined in IEEE 802.3 Clause 48
to discard ∥S dp ∥, ∥T 0 ∥, and ∥I∥ columns in the input data channel and to deinterleave ∥C∥ and ∥D∥ columns in the input data channel.
6. The digital interface translator of claim 1 , wherein the output digital interface standard is the HDMI (high definition multimedia interface) standard.
7. The digital interface translator of claim 6 , wherein the digital interface translator is configured to utilize the following definitions:
∥C 0 ∥=/K 2 x.y/I/I/I/
∥C 1 ∥=/K 1 x.y/K 2 x.y/I/I/
∥C 2 ∥=/K 0 x.y/K 1 x.y/K 2 x.y/I
∥C 3 ∥=/K 0 x.y/K 1 x.y/K 2 x.y/K 0 x.y/, /K 1 x.y/K 2 x.y/K 0 x.y/K 1 x.y/, /K 2 x.y/K 0 x.y/K 1 x.y/K 2 x.y/
∥D∥=/D 0 x.y/D 1 x.y/D 2 x.y/D 0 x.y/, /D 1 x.y/D 2 x.y/D 0 x.y/D 1 x.y/, /D 2 x.y/D 0 x.y/D 1 x.y/D 2 x.y/
|S hv ∥=/S/D0.0/D0.0/D0.1/, SOP (start of packet) for VDC (video data coding) data
∥S ht ∥=/S/D0.0/D0.0/D1.1/, SOP (start of packet) for Data Island TERC4 (transition minimized differential signaling error reduction coding) data
∥T 0 ∥=/T/I/I/I/, defined in IEEE 802.3 Clause 48
∥I∥=/I/I/I/I/, defined in IEEE 802.3 Clause 48
to discard ∥S hv ∥, ∥S ht ∥, ∥T 0 ∥, and ∥I∥ columns in the input data channel and to deinterleave ∥C∥ and ∥D∥ columns in the input data channel.
8. The digital interface translator of claim 1 , wherein the output digital interface standard is the DVI (digital visual interface) standard.