IP Library Granted Patent US 8,711,027
Granted Patent B1
US 8,711,027 · App. 13/681,371 · Granted Apr 29, 2014

Analog-to-digital converter with input voltage biasing DC level of resonant oscillator

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Quick Facts
Patent No.
US 8,711,027
App. No.
13/681,371
Granted
Apr 29, 2014
Kind
B1
Abstract

An analog-to-digital converter is disclosed comprising a resonant oscillator comprising an input operable to receive an analog input signal and an output operable to output an oscillating signal. A DC offset detector detects a DC offset in the oscillating signal caused by the analog input signal, wherein the DC offset is converted into a digital output signal representing the analog input signal.

Claims (41)

1. An analog-to-digital converter comprising:

a resonant oscillator comprising an input operable to receive an analog input signal and an output operable to output an oscillating signal; and

a DC offset detector operable to detect a DC offset in the oscillating signal caused by the analog input signal, wherein the DC offset is converted into a digital output signal representing the analog input signal.

2. The analog-to-digital converter as recited in claim 1 , wherein the resonant oscillator comprises a ceramic resonator.

3. The analog-to-digital converter as recited in claim 1 , wherein the resonant oscillator comprises a crystal.

4. The analog-to-digital converter as recited in claim 1 , wherein the resonant oscillator comprises a silicon oscillator.

5. The analog-to-digital converter as recited in claim 1 , wherein the DC offset detector is operable to:

measure a first time the oscillating signal is above a threshold;

measure a second time the oscillating signal is below the threshold; and

detect the DC offset based on a time delta between the first time and the second time.

6. The analog-to-digital converter as recited in claim 5 , wherein the DC offset detector is further operable to:

accumulate a number of the time deltas over a number of cycles of the oscillating signal; and

detect the DC offset based on the accumulated time deltas.

7. The analog-to-digital converter as recited in claim 6 , wherein:

the DC offset detector is further operable to generate a bias signal in response to the accumulated time deltas; and

the bias signal is operable to drive the DC offset in the oscillating signal toward zero.

8. The analog-to-digital converter as recited in claim 7 , wherein the bias signal has substantially no effect on an input impedance of the resonant oscillator.

9. The analog-to-digital converter as recited in claim 8 , wherein the DC offset detector comprises a current source and a current sink operable to generate the bias signal.

10. The analog-to-digital converter as recited in claim 5 , wherein the DC offset detector is further operable to Vernier a clock signal used to generate the first and second times in order to increase a resolution of the analog-to-digital conversion.

11. The analog-to-digital converter as recited in claim 5 , wherein the DC offset detector is further operable to dither the threshold in order to increase a resolution of the analog-to-digital conversion.

12. A method of converting an analog signal into a digital signal, the method comprising:

biasing a resonant oscillator with the analog input signal to generate an oscillating signal;

detecting a DC offset in the oscillating signal caused by the analog input signal, wherein the DC offset; and

converting the DC offset into the digital signal representing the analog signal.

13. The method as recited in claim 12 , wherein the resonant oscillator comprises a ceramic resonator.

14. The method as recited in claim 12 , wherein the resonant oscillator comprises a crystal.

15. The method as recited in claim 12 , wherein the resonant oscillator comprises a silicon oscillator.

16. The method as recited in claim 12 , wherein detecting the DC offset comprises:

measuring a first time the oscillating signal is above a threshold;

measuring a second time the oscillating signal is below the threshold; and

detecting the DC offset based on a time delta between the first time and the second time.

17. The method as recited in claim 16 , wherein detecting the DC offset further comprises:

accumulating a number of the time deltas over a number of cycles of the oscillating signal; and

detecting the DC offset based on the accumulated time deltas.

18. The method as recited in claim 17 , wherein:

generating a bias signal in response to the accumulated time deltas; and

drive the DC offset in the oscillating signal toward zero in response to the bias signal.

19. The method as recited in claim 18 , wherein the bias signal has substantially no effect on an input impedance of the resonant oscillator.

20. The method as recited in claim 19 , further comprising generating the bias signal using a current source and a current sink.

21. The method as recited in claim 16 , wherein detecting the DC offset further comprises Verniering a clock signal used to generate the first and second times in order to increase a resolution of the analog-to-digital conversion.

22. The method as recited in claim 16 , wherein detecting the DC offset further comprises dithering the threshold in order to increase a resolution of the analog-to-digital conversion.

Assignments (8)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2012
From: BENNETT, GEORGE J.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 029324/0606 →