Isolation interface circuit for power management

1. An isolation interface circuit, comprising:

a transmitting circuit configured to receive a first serial interface signal and a second serial interface signal for generating a differential polarity pulse signal; and

a receiving circuit configured to receive the differential polarity pulse signal for generating the first serial interface signal and the second serial interface signal;

wherein the differential polarity pulse signal is generated in response to the first serial interface signal and the second serial interface signal; the first serial interface signal and the second serial interface signal are generated in accordance with the differential polarity pulse signal; in a period, only one of the transmitting circuit and the receiving circuit can be enabled,

in which the first serial interface signal and the second serial interface signal develop a frame including a start bit, a stop bit and data.

2. The circuit as claimed in claim 1 , in which the differential polarity pulse signal develop a frame includes a start signal, a stop signal and data signal.

3. The circuit as claimed in claim 1 , in which the polarity of the differential polarity pulse signal represents the logic-high or the logic-low.

4. The circuit as claimed in claim 1 , in which a number of the differential polarity pulse signal in a specific period represents the start signal, the stop signal or the data signal.

5. The circuit as claimed in claim 1 , in which a number and a polarity of the differential polarity pulse signal in a specific period represent the start signal or the stop signal.

6. The circuit as claimed in claim 1 , in which the first serial interface signal can be parallel connected to another first serial interface signal of another isolation interface circuit; and the second serial interface signal can be parallel connected to another second serial interface signal of another isolation interface circuit.

7. The circuit as claimed in claim 1 , in which the differential polarity pulse signal can be parallel connected to another differential polarity pulse signal of another isolation interface circuit through a pair of capacitors.

8. The circuit as claimed in claim 1 , in which the differential polarity pulse signal can be parallel connected to another differential polarity pulse signal of another isolation interface circuit through a transformer.

9. The circuit as claimed in claim 1 , in which the isolation interface circuit is utilized in a battery management system.

10. The circuit as claimed in claim 1 , in which the isolation interface circuit is utilized in a battery management circuit; the first battery management circuit can communicate with the second battery management circuit through a pair of capacitors.

11. The circuit as claimed in claim 1 , in which the isolation interface circuit is utilized in a battery management circuit; the first battery management circuit can communicate with the second battery management circuit through a transformer.

12. The circuit as claimed in claim 1 , in which the pulse width of the differential polarity pulse signal is shorter than 300 nsec.

13. The circuit as claimed in claim 1 , in which the output of the differential polarity pulse signal is only enabled within a specific time; after the specific time, the output of the differential polarity pulse signal become a high impedance.

14. The circuit as claimed in claim 1 , in which an input node of the differential polarity pulse signal is coupled to an output node of a low-pass filter.