Voltage level shift circuits and methods
View Patent ↗In one embodiment, the present invention includes a charge pump circuit. The charge pump circuit comprises a plurality of terminals, a plurality of switches for selectively coupling the plurality of terminals, and a control circuit. A first input terminal receives a first reference voltage and a second input terminal receives a second reference voltage. First, second, third, and fourth flying capacitor terminals and the first and second input terminals are selectively coupled together in different configurations. The control circuit selects the switches to actuate according to a cycling of at least three phases of configuration. The cycling shifts the first and second reference voltages to provide dual power supply rails.
1. An electrical circuit, comprising
a first terminal for engaging a first reference voltage;
a second terminal for engaging a second reference voltage, which is different from the first reference voltage;
a first capacitor and a second capacitor;
a plurality of switches operable to selectably connecting the first reference voltage and the second reference voltage to the first capacitor and the second capacitor; and
a third capacitor having two terminals operable to be connected by the plurality of switches to the first capacitor and the second capacitor to generate at one of the two terminals a voltage outside the voltage range between the first reference voltage and the second reference voltage and at the other one of the two terminals a voltage inside the voltage range between and not including the first reference voltage and the second reference voltage.
2. The electrical circuit of claim 1 , in which the switches are integrated in one integrated circuit chip.
3. The electrical circuit of claim 2 , in which the first capacitor and the second capacitor and the third capacitor are electrically externally connected to the integrated circuit chip.
4. The integrated circuit chip of claim 2 , further comprising a control circuit for selectably activating and deactivating the plurality of switches.
5. The control circuit of claim 4 , further comprising a terminal for engaging a clock signal.
6. The electrical circuit of claim 5 , further comprising an oscillator for supplying the clock signal engaging the control circuit.
7. The electrical circuit of claim 1 , in which the first capacitor and the second capacitor are of same capacitance.
8. The integrated circuit of claim 1 , in which the plurality of switches are operable in one configuration connecting the first capacitor and the second capacitor in series and in a second and different configuration connecting the first capacitor and the second capacitor in parallel.
9. The integrated circuit of claim 1 , in which the plurality of switches are further operable to connect the third capacitor between the first capacitor and the second capacitor in a configuration where a positively charged end of the first capacitor is electrically shorted to a negatively charged end of the second capacitor.
10. A integrated circuit chip, comprising:
a plurality of switches selectably operable to urge on a first capacitor and a second capacitor a first reference voltage and a second reference voltage, which is at a different voltage from the first reference voltage, such that a fraction of the voltage difference is maintained across the first capacitor and across the second capacitor; and
the plurality of switches selectably operable to connect a third capacitor having two terminals to the first capacitor and the second capacitor to yield a voltage at one of the two terminals outside the voltage range between the first reference voltage and the second reference voltage, and a voltage at the other terminal of the two terminals inside the voltage range between but not including the first reference voltage and the second reference voltage.
11. The integrated circuit chip of claim 10 , further comprising a control circuit for selectably activating and deactivating the plurality of switches.
12. The control circuit of claim 11 , further comprising a terminal for engaging a clock signal.
13. The integrated circuit chip of claim 10 , in which the plurality of switches are operable in one configuration connecting the first capacitor and the second capacitor in series and in a second and different configuration connecting the first capacitor and the second capacitor in parallel.
14. The integrated circuit chip of claim 13 , in which the plurality of switches are further operable to connect the third capacitor between the first capacitor and the second capacitor in a configuration where a positively charged end of the first capacitor is electrically shorted to a negatively charged end of the second capacitor.
15. The integrated circuit chip of claim 14 , in which the voltage range is between a positive voltage and a ground potential.
16. The integrated circuit chip of claim 15 , in which one end of the third capacitor is at a voltage of half the voltage difference above the ground potential and another end of the third capacitor is at a voltage of half the voltage difference below the ground potential.