IP Library Granted Patent US 8,669,555
Granted Patent B2
US 8,669,555 · App. 13/684,369 · Granted Mar 11, 2014

Semiconductor device

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Quick Facts
Patent No.
US 8,669,555
App. No.
13/684,369
Granted
Mar 11, 2014
Kind
B2
Abstract

Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.

Claims (30)

1. A semiconductor device comprising:

an electrode pad having a probe region and a non-probe region,

a pad metal disposed under the probe region, the pad metal electrically connected to the electrode pad, and

a metal layer disposed under the non-probe region,

wherein the pad metal and the metal layer are disposed in a same layer, and

a plurality of the electrode pads are arranged in a zigzag pattern.

2. The device of claim 1 , wherein the electrode pad and the pad metal are connected by a connector.

3. The device of claim 2 , wherein the connector is made of metal.

4. The device of claim 3 , wherein the connector is smaller than the pad metal.

5. The device of claim 4 , wherein an interlayer insulating film is disposed between the electrode pad and the metal layer.

6. The device of claim 5 , wherein the plurality of electrode pads surround an internal circuit in plan view.

7. The device of claim 6 , further comprising a bump disposed on the electrode pad.

8. The device of claim 7 , wherein the metal layer is not electrically connected to the electrode pad.

9. The device of claim 8 , wherein the probe region is placed in a region within 20 μm from a center line of the electrode pad extending substantially in parallel with a longitudinal axis of the metal layer, and the non-probe region is placed in a region of the electrode pad other than the probe region.

10. The device of claim 1 , wherein there is no other metal layer disposed between said metal layer and said electrode pad.

11. A semiconductor device comprising:

an electrode pad,

a probe mark left on the electrode pad,

a pad metal disposed under the probe mark, the pad metal electrically connected to the electrode pad, and

a metal layer disposed under the electrode pad in an area outside of the probe mark in plan view,

wherein the pad metal and the metal layer are disposed in a same layer, and

a plurality of the electrode pads are arranged in a zigzag pattern.

12. The device of claim 11 , wherein the electrode pad and the pad metal are connected by a connector.

13. The device of claim 12 , wherein the connector is made of metal.

14. The device of claim 13 , wherein the connector is smaller than the pad metal.

15. The device of claim 14 , wherein an interlayer insulating film is disposed between the electrode pad and the metal layer.

16. The device of claim 15 , wherein the plurality of electrode pads surround an internal circuit in plan view.

17. The device of claim 16 , further comprising a bump disposed on the electrode pad.

18. The device of claim 17 , wherein the metal layer is not electrically connected to the electrode pad.

19. The device of claim 11 , wherein there is no other metal layer disposed between said metal layer and said electrode pad.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →