Granted Patent B2

US 9,076,500 · App. 13/685,192 · Granted Jul 7, 2015

Abstract

Claims (79)

1. A memory module comprising:

a module substrate having first and second main surfaces opposite to each other, the first main surface having first and second memory mounting areas, one of the first and second main surfaces having a register mounting area located between the first and second memory mounting areas in a planar view;

a plurality of data connectors formed on the module substrate;

a plurality of memory devices including a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area; and

a plurality of data register buffers mounted on the register mounting area, the data register buffers transferring write data supplied from the data connectors to the memory devices, and transferring read data supplied from the memory devices to the data connectors, wherein

the first memory devices are arranged in a first direction in the first memory mounting area,

the second memory devices are arranged in the first direction in the second memory mounting area,

the data register buffers are arranged in the first direction in the register mounting area, and

each of the data register buffers and associated ones of the first and second memory devices connected thereto are arranged in a second direction crossing the first direction in the planar view.

2. The memory module as claimed in claim 1 , wherein the first memory devices and the second memory devices are activated in common.

3. The memory module as claimed in claim 1 , wherein the first memory devices and the second memory devices are mounted in 180° different directions.

4. The memory module as claimed in claim 1 , wherein

the second main surface of the module substrate has third and fourth memory mounting areas,

the plurality of memory devices further include a plurality of third memory devices that are mounted on the third memory mounting area and a plurality of fourth memory devices that are mounted on the fourth memory mounting area,

the first memory devices and the third memory devices are mounted in overlapping positions in the planar view,

the second memory devices and the fourth memory devices are mounted in overlapping positions in the planar view, and

each of data register buffers and associated ones of the third and fourth memory devices connected thereto are arranged in a second direction crossing the first direction in the planar view.

5. The memory module as claimed in claim 4 , wherein

the third memory devices and the fourth memory devices are activated in common, and

the first and second memory devices and the third and fourth memory devices are exclusively activated.

6. The memory module as claimed in claim 4 , wherein

the first memory devices and the second memory devices are mounted in 180° different directions; and

the third memory devices and the fourth memory devices are mounted in 180° different directions.

7. The memory module as claimed in claim 5 , wherein

the first main surface of the module substrate further has fifth and sixth memory mounting areas,

the second main surface of the module substrate further has seventh and eighth memory mounting areas,

the plurality of memory devices further include a plurality of fifth memory devices that are mounted on the fifth memory mounting area, a plurality of sixth memory devices that are mounted on the sixth memory mounting area, a plurality of seventh memory devices that are mounted on the seventh memory mounting area, and a plurality of eighth memory devices that are mounted on the eighth memory mounting area,

the register mounting area is arranged between the fifth and sixth memory mounting areas in the planar view,

the fifth memory devices and the seventh memory devices are mounted in overlapping positions in the planar view,

the sixth memory devices and the eighth memory devices are mounted in overlapping positions in the planar view, and each of the data register buffers and associated ones of the fifth to eighth memory devices connected thereto are arranged in the second direction in the planar view.

8. The memory module as claimed in claim 7 , wherein

the fifth memory devices and the sixth memory devices are activated in common,

the seventh memory devices and the eighth memory devices are activated in common,

the first and second devices, the third and fourth memory devices, the fifth and sixth memory devices, and the seventh and eighth memory devices are exclusively activated.

9. The memory module as claimed in claim 7 , wherein

the fifth memory mounting area is arranged between the first memory mounting area and the register mounting area in the planar view, and

the second memory mounting area is arranged between the sixth memory mounting area and the register mounting area in the planar view.

10. The memory module as claimed in claim 7 , wherein

the first memory devices and the fifth memory devices are mounted in 180° different directions,

the second memory devices and the sixth memory devices are mounted in 180° different directions,

the third memory devices and the seventh memory devices are mounted in 180° different directions, and

the fourth memory devices and the eighth memory devices are mounted in 180° different directions.

11. The memory module as claimed in claim 7 , further comprising first and second command address register buffers that are mounted on the module substrate, wherein

the first command address register buffer supplies a command address signal to the first to fourth memory devices, and

the second command address register buffer supplies a command address signal to the fifth to eighth memory devices.

12. The memory module as claimed in claim 1 , wherein each of the memory devices includes one or more memory chips.

13. A memory module comprising:

a module substrate having first and second main surfaces opposite to each other, the first main surface having first and second memory mounting areas, one of the first and second main surfaces having a register mounting area located between the first and second memory mounting areas in a planar view;

a plurality of data connectors formed on the module substrate;

a plurality of memory devices including a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area; and

a plurality of data register buffers mounted on the register mounting area, the data register buffers transferring write data supplied from the data connectors to the memory devices, and transferring read data supplied from the memory devices to the data connectors,

wherein

the second main surface of the module substrate has third and fourth memory mounting areas,

the plurality of memory devices further include a plurality of third memory devices that are mounted on the third memory mounting area and a plurality of fourth memory devices that are mounted on the fourth memory mounting area,

the first memory devices and the third memory devices are mounted in overlapping positions in the planar view,

the second memory devices and the fourth memory devices are mounted in overlapping positions in the planar view,

each of data register buffers and associated ones of the third and fourth memory devices connected thereto are arranged in a second direction crossing a first direction in the planar view,

the first main surface of the module substrate further has fifth and sixth memory mounting areas,

the second main surface of the module substrate further has seventh and eighth memory mounting areas,

the plurality of memory devices further include a plurality of fifth memory devices that are mounted on the fifth memory mounting area, a plurality of sixth memory devices that are mounted on the sixth memory mounting area, a plurality of seventh memory devices that are mounted on the seventh memory mounting area, and a plurality of eighth memory devices that are mounted on the eighth memory mounting area,

the register mounting area is arranged between the fifth and sixth memory mounting areas in the planar view,

the fifth memory devices and the seventh memory devices are mounted in overlapping positions in the planar view,

the sixth memory devices and the eighth memory devices are mounted in overlapping positions in the planar view, and

each of the data register buffers and associated ones of the fifth to eighth memory devices connected thereto are arranged in the second direction in the planar view.

14. The memory module as claimed in claim 13 , wherein

the fifth memory devices and the sixth memory devices are activated in common,

the seventh memory devices and the eighth memory devices are activated in common,

the first and second devices, the third and fourth memory devices, the fifth and sixth memory devices, and the seventh and eighth memory devices are exclusively activated.

15. The memory module as claimed in claim 13 , wherein

the fifth memory mounting area is arranged between the first memory mounting area and the register mounting area in the planar view, and

the second memory mounting area is arranged between the sixth memory mounting area and the register mounting area in the planar view.

16. The memory module as claimed in claim 13 , wherein

the first memory devices and the fifth memory devices are mounted in 180° different directions,

the second memory devices and the sixth memory devices are mounted in 180° different directions,

the third memory devices and the seventh memory devices are mounted in 180° different directions, and

the fourth memory devices and the eighth memory devices are mounted in 180° different directions.

17. The memory module as claimed in claim 13 , further comprising first and second command address register buffers that are mounted on the module substrate, wherein

the first command address register buffer supplies a command address signal to the first to fourth memory devices, and

the second command address register buffer supplies a command address signal to the fifth to eighth memory devices.

Assignments (6)