Memory controller, memory system, and memory write method

1. A memory controller for controlling a nonvolatile memory, comprising:

a memory interface that has multiple channels and carries out writing into the nonvolatile memory through each of the channels;

a data buffer;

an ECC (error correcting code) encoder for applying an error correction encoding processing on write data to be written into the nonvolatile memory, thereby generating ECC data;

a channel allocation part for allocating the channels to the write data and the ECC data based on a write data format of the nonvolatile memory;

a write data reception processing part that stores the write data in the data buffer and outputs the write data to the ECC encoder;

a channel scheduler for transferring the write data and the ECC data to the channels of the memory interface as allocated by the channel allocation part, wherein subsequent write data are transferred to each of the channels which has finished carrying out writing of the write data allocated to the channel into the nonvolatile memory without waiting for writing of the corresponding ECC data to finish, such that a period during which the write data is transferred overlaps a period during which error correction encoding processing is applied on the write data; and

a write command issuing part that (1) specifies a unit size of write data transferred to the memory interface, (2) receives a channel allocation result from the channel allocation part, and (3) issues a write command to instruct the channel scheduler to write the write data, upon determining that processing of write data equal in size to the unit size of the write data has completed,

wherein the unit size of the write data is smaller than a unit size of error correction data, the error correction data including both the ECC data and the write data corresponding to the ECC data.

2. The memory controller according to claim 1 , wherein

the write data are distributed to two or more channels.

3. The memory controller according to claim 1 , wherein

data of the unit size of write data includes data that are written into a single channel.

4. The memory controller according to claim 1 , wherein the ECC encoder comprises:

an ECC buffer for storing the ECC data, and

a buffer management part that updates information about the ECC buffer in which the ECC data are stored to indicate a vacant area upon being notified that the ECC data have been transferred to the memory interface.

5. The memory controller according to claim 4 , wherein the ECC encoder further comprises:

a start detection part that detects a start position of the write data as a source of the ECC data, and determines a start address in the ECC buffer for storing the ECC data based on the information indicating the vacant area of the ECC buffer;

an ECC calculation part that (1) receives, as input data, the write data at a prescribed data unit, (2) performs error correction encoding processing using the input data at the start position detected by the start detection part as a start input, (3) stores a result of the error correction encoding processing in the start address of the ECC buffer, (4) updates the ECC buffer by applying the error correction encoding processing each time input data are added thereafter, and (5) updates the value of an encoding counter as the error correction encoding processing is applied to each input data; and

an end detection part for notifying the channel allocation part of an end of the ECC data generation.

6. The memory controller according to claim 5 , wherein, the end of the ECC data generation is detected based on the number of input data as a source of the ECC data and the counter value of the encoding counter, and the channel allocation part allocates the channels to which the ECC generation end has been notified to the ECC data.

7. A memory system comprising:

a nonvolatile memory;

a memory interface that has multiple channels and carries out writing into the nonvolatile memory through each of the channels;

a data buffer;

an ECC (error correcting code) encoder for applying an error correction encoding processing on write data to be written into the nonvolatile memory, thereby generating ECC data;

a channel allocation part for allocating the channels to the write data and the ECC data based on a write data format of the nonvolatile memory;

a write data reception processing part that stores the write data in the data buffer and outputs the write data to the ECC encoder; and

a channel scheduler for transferring the write data and the ECC data to the channels of the memory interface as allocated by the channel allocation part, wherein subsequent write data are transferred to each of the channels which has finished carrying out writing of the write data allocated to the channel into the nonvolatile memory without waiting for writing of the corresponding ECC data to finish, such that a period during which the write data is transferred overlaps a period during which error correction encoding processing is applied on the write data; and

a write command issuing part that (1) specifies a unit size of write data that are transferred to the memory interface, (2) receives a channel allocation result from the channel allocation part, and (3) issues a write command to instruct the channel scheduler to write the write data, upon determining that processing of write data equal in size to the unit size of the write data has completed,

wherein the unit size of the write data is smaller than a unit size of error correction data, the error correction data including both the ECC data and the write data corresponding to the ECC data.

8. The memory system according to claim 7 , wherein

the write data are distributed to two or more channels.

9. The memory system according to claim 7 , wherein

data of the unit size of write data includes data that are written into a single channel.

10. The memory system according to claim 7 , wherein the ECC encoder comprises:

an ECC buffer for storing the ECC data, and

a buffer management part that updates information about the ECC buffer in which the ECC data are stored to indicate a vacant area upon being notified that the ECC data have been transferred to the memory interface.

11. The memory system according to claim 10 , wherein the ECC encoder further comprises:

a start detection part that detects a start position of the write data as a source of the ECC data, and determines a start address in the ECC buffer for storing the ECC data based on the information indicating the vacant area of the ECC buffer;

an ECC calculation part that (1) receives, as input data, the write data at a prescribed data unit, (2) performs error correction encoding processing using the input data at the start position detected by the start detection part as a start input, (3) stores a result of the error correction encoding processing in the start address of the ECC buffer, (4) updates the ECC buffer by applying the error correction encoding processing each time input data are added thereafter, and (5) updates the value of an encoding counter as the error correction encoding processing is applied to each input data; and

an end detection part for notifying the channel allocation part of an end of the ECC data generation.

12. The memory system according to claim 11 , wherein, the end of the ECC data generation is detected based on the number of input data as a source of the ECC data and the counter value of the encoding counter, and the channel allocation part allocates the channels to which the ECC generation end has been notified to the ECC data.

13. A method of writing to a memory system including a nonvolatile memory, which can carry out reading and writing through multiple channels, and an ECC (error correcting code) encoder, the method comprising the steps of:

storing write data, which are to be written into the nonvolatile memory, in a data buffer and supplying the write data into an ECC encoder;

applying an error correction encoding processing on the write data to generate ECC data;

allocating the channels to the write data and the ECC data based on a write data format of the nonvolatile memory;

specifying a unit size of write data transferred to the channels;

issuing a write command to write the write data, upon determining that processing of write data equal in size to the unit size of the write data has completed, wherein the unit size of the write data is smaller than a unit size of error correction data, the error correction data including both the ECC data and the write data corresponding to the ECC data; and

transferring the write data stored in the data buffer and the ECC data to the channels as allocated,

wherein subsequent write data are transferred to each of the channels which has finished carrying out writing of the write data allocated to the channel into the nonvolatile memory without waiting for writing of the corresponding ECC data to finish, such that a period during which the write data is transferred overlaps a period during which error correction encoding processing is applied on the write data.

14. The method of claim 13 , wherein the write data are transferred to two or more channels and the ECC data are transferred to one channel.