IP Library Granted Patent US 8,736,378
Granted Patent B1
US 8,736,378 · App. 13/690,295 · Granted May 27, 2014

Reconfigureable output matching network for multi band RF power amplifier

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Quick Facts
Patent No.
US 8,736,378
App. No.
13/690,295
Granted
May 27, 2014
Kind
B1
Abstract

An output matching network comprising a plurality of impedance matching circuits. The inputs of each of the plurality of impedance matching circuits are connected to a first input of the output matching network. The outputs of each of the plurality of impedance matching circuits are connected to a plurality of first outputs of the output matching network. One of the plurality of impedance matching circuits is active at a given time. The active impedance matching circuit of the plurality of impedance matching circuits exhibits a first input impendence at a first frequency band. Each inactive impedance matching circuit of the plurality of impedance matching circuits exhibits a second input impedance at the first frequency band. The second input impendence is at least 10 times greater than the first input impendence.

Claims (69)

1. An output matching network comprising:

a first input and a plurality of first outputs;

a plurality of impedance matching circuits, each of the plurality of impedance matching circuits comprising an input and an output, wherein:

the inputs of each of the plurality of impedance matching circuits are connected to the first input,

the outputs of each of the plurality of impedance matching circuits are connected to the plurality of first outputs,

one of the plurality of impedance matching circuits is active at a given time,

the active impedance matching circuit of the plurality of impedance matching circuits exhibits a first input impendence at a first frequency band,

each inactive impedance matching circuit of the plurality of impedance matching circuits exhibits a second input impedance at the first frequency band, and wherein the second input impendence is at least 10 times greater than the first input impendence.

2. The output matching network of claim 1 , wherein at least one of the inactive impedance matching circuit of the plurality of impedance matching circuits exhibits a first input harmonic impedance at twice the first frequency band.

3. The output matching network of claim 2 , wherein the first input harmonic impedance can be an open circuit or a short circuit.

4. The output matching network of claim 1 , wherein each impendence matching circuit of the plurality of impedance matching circuits comprises one or more of a plurality of inductors, a plurality of capacitors, one or more transmission lines, or a plurality of switches.

5. The output matching network of claim 4 , wherein the one or more transmission lines and the plurality of capacitors comprise at least one of: lumped elements and distributed elements.

6. The output matching network of claim 1 , wherein each of the plurality of impedance matching circuits comprises:

a first, a second, and a third inductor coupled in series;

a first capacitor coupled in parallel to the second inductor;

a second capacitor coupled in shunt between a common terminal of the second and the third inductors, and a ground terminal; and

a third capacitor coupled in shunt between an output of the third inductor and the ground terminal.

7. The output matching network of claim 6 , wherein each of the plurality of impedance matching circuits comprises:

a first switch coupled in series to the first capacitor; and

a second switch coupled in series to the third capacitor, wherein the first switch and the second switch are closed when the impedance matching circuit is inactive, and the first switch and the second switch are open when the impedance matching circuit is active.

8. The output matching network of claim 1 , wherein each of the plurality of impedance matching circuits comprises:

a plurality of transmission lines coupled in series;

a directional coupler coupled to at least one of the plurality of transmission lines;

a plurality of capacitors coupled to the plurality of transmission lines; and

a plurality of switches, wherein the plurality of switches are closed when the impedance matching circuit is inactive and the plurality of switches are open when the impedance matching circuit is active.

9. A multi-band power amplification system comprising:

a second input and a plurality of second outputs;

a power amplifier having an input and an output; and

an output matching network having an input and a plurality of outputs, wherein the input of the power amplifier is coupled to the second input, the input of the output matching network is coupled to the output of the power amplifier, the plurality of outputs of the output matching network is coupled to the plurality of second outputs, and wherein the output matching network comprises:

a plurality of impedance matching circuits, each of the plurality of impedance matching circuits comprising an input and an output, wherein:

the inputs of the plurality of impedance matching circuits are connected to the input of the output matching network;

the outputs of the plurality of impedance matching circuits are connected to the plurality of outputs of the output matching network;

one of the plurality of impedance matching circuits is active at a given time,

the active impedance matching circuit of the plurality of impedance matching circuits exhibits a first input impendence at a first frequency band,

each inactive impedance matching circuit of the plurality of impedance matching circuits exhibits a second input impedance at the first frequency band, and wherein the second input impendence is at least 10 times greater than the first input impendence.

10. The multi-band power amplification system of claim 9 , wherein at least one of the inactive impedance matching circuit of the plurality of impedance matching circuits exhibits a first input harmonic impedance at twice the first frequency band.

11. The multi-band power amplification system of claim 10 , wherein the first input harmonic impedance is at least one of: an open circuit and a short circuit.

12. The multi-band power amplification system of claim 9 , wherein each impendence matching circuit of the plurality of impedance matching circuits comprises one or more of a plurality of inductors, a plurality of capacitors, one or more transmission lines, or a plurality of switches.

13. The multi-band power amplification system of claim 9 , wherein each of the plurality of impedance matching circuits comprises:

a first, second, and third inductors coupled in series;

a first capacitor coupled in parallel to the second inductor;

a second capacitor coupled in shunt between a common terminal of the second and the third inductors, and a ground terminal; and

a third capacitor coupled in shunt between an output of the third inductor and the ground terminal.

14. The multi-band power amplification system of claim 13 , wherein each of the plurality of impedance matching circuits comprises:

a first switch coupled in series to the first capacitor; and

a second switch coupled in series to the third capacitor; wherein the first switch and the second switch are closed when the impedance matching circuit is inactive, and the first switch and the second switch are open when the impedance matching circuit is active.

15. The multi-band power amplification system of claim 9 , wherein at least one of the plurality of impedance matching circuits comprises:

a plurality of transmission lines coupled in series to each other;

a directional coupler coupled to at least one of the plurality of transmission lines;

a plurality of capacitors coupled to the plurality of transmission lines; and

a plurality of switches, wherein the plurality of switches are closed when the impedance matching circuit is inactive and the plurality of switches are open when the impedance matching circuit is active.

16. A multi-band power amplification system comprising:

a second input and a plurality of second outputs;

a power amplifier having an input and an output; and

an output matching network having an input and a plurality of outputs, wherein the input of the power amplifier is coupled to the second input, the input of the output matching network coupled to the output of the power amplifier,

the plurality of outputs of the output matching network being coupled to the plurality of second outputs, and wherein the output matching network comprises:

a plurality of impedance matching circuits, each of the plurality of impedance matching circuits comprising an input and an output, wherein:

the inputs of each of the plurality of impedance matching circuits are connected to the input of the output matching network,

the outputs of each of the plurality of impedance matching circuits are connected to the outputs of the output matching network,

the output matching network further comprising a plurality of impedance matching circuits, wherein each of the plurality of impendence matching circuits comprising:

an input and an output; a first, second, and third inductors coupled in series; a first capacitor coupled in parallel to the second inductor; a second capacitor coupled in shunt between a common terminal of the second and the third inductors, and a first ground terminal; a third capacitor coupled in shunt between an output of the third inductor and a second ground terminal; a first switch coupled in series to the first capacitor; and a second switch coupled in series to the third capacitor, wherein the first switch and the second switch are closed when the impedance matching circuit is inactive and the first switch and the second switch are open when the impedance matching circuit is active;

wherein one of the plurality of impedance matching circuits is active at a given time, the active output impedance matching circuit of the plurality of impedance matching circuits exhibits a first impendence at a first frequency band, each inactive impedance matching circuit of the plurality of impedance matching circuits exhibits a second impedance at the first frequency band, and wherein the second impendence is at least 10 times greater than the first impendence, at least one of the inactive impedance matching circuit of the plurality of impedance matching circuits exhibits a first input harmonic impedance at twice the first frequency band, and wherein the first input harmonic impedance can be an open circuit or a short circuit.

17. The multi-band power amplification system of claim 13 further comprising:

an input matching network having a plurality of third inputs and a third output, wherein the third output is coupled to the input of the power amplifier; and

a plurality of impedance matching circuits, each of the plurality of impedance matching circuits comprising an input and an output, wherein:

the inputs of each of the plurality of impedance matching circuits are connected to the third inputs,

the outputs of each of the plurality of impedance matching circuits are connected to the third output,

one of the plurality of impedance matching circuits is active at a given time,

each of the plurality of impedance matching circuits having a series switch, wherein the series switch is closed when the impedance matching circuit is active and the series switch is open when the impedance matching circuit is inactive.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2017
From: II-VI OPTOELECTRONIC DEVICES, INC.
To: SKYWORKS SOLUTIONS, INC.
Reel/Frame 042551/0708 →
CHANGE OF NAME Recorded May 1, 2017
From: ANADIGICS, INC.
To: II-VI OPTOELECTRONIC DEVICES, INC.
Reel/Frame 042381/0761 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUS NUMBER 6790900 AND REPLACE IT WITH 6760900 PREVIOUSLY RECORDED ON REEL 034056 FRAME 0641. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Nov 21, 2016
From: ANADIGICS, INC.
To: SILICON VALLEY BANK
Reel/Frame 040660/0967 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 037973 FRAME: 0226. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded May 18, 2016
From: ANADIGICS, INC.
To: II-VI INCORPORATED
Reel/Frame 038744/0835 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2016
From: II-VI INCORPORATED
To: ANADIGICS, INC.
Reel/Frame 038119/0312 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Mar 1, 2016
From: ANADIGICS, INC.
To: II-IV INCORPORATED
Reel/Frame 037973/0226 →
RELEASE OF SECURITY INTEREST Recorded Mar 1, 2016
From: SILICON VALLEY BANK
To: ANADIGICS, INC.
Reel/Frame 037973/0133 →
SECURITY AGREEMENT Recorded Oct 27, 2014
From: ANADIGICS, INC.
To: SILICON VALLEY BANK
Reel/Frame 034056/0641 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2012
From: HAU, GARY
To: ANADIGICS, INC.
Reel/Frame 029383/0170 →