IP Library Granted Patent US 8,895,431
Granted Patent B2
US 8,895,431 · App. 13/690,784 · Granted Nov 25, 2014

Method for fabricating semiconductor device

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Quick Facts
Patent No.
US 8,895,431
App. No.
13/690,784
Granted
Nov 25, 2014
Kind
B2
Abstract

A method for fabricating a semiconductor device includes: forming an interlayer insulating film on a substrate; forming a first hard mask formation film on the interlayer insulating film; altering the first hard mask formation film; after the altering of the first hard mask formation film, transferring an interconnect groove pattern to the altered first hard mask formation film to form a first hard mask made of the altered first hard mask formation film; and etching the interlayer insulating film using the first hard mask to form an interconnect groove in the interlayer insulating film. The first hard mask formation film is made of a metal film or a metallic compound film.

Claims (26)

1. A method for fabricating a semiconductor device, the method comprising:

forming an interlayer insulating film on a substrate;

sequentially forming a first hard mask formation film and a second hard mask formation film on the interlayer insulating film;

transferring an interconnect groove pattern to the first and second hard mask formation films to form a first hard mask made of the first hard mask formation film and a second hard mask made of the second hard mask formation film; and

etching the interlayer insulating film using the first and second hard masks to form an interconnect groove in the interlayer insulating film, wherein

the first and second hard mask formation films contain an identical metal element.

2. The method of claim 1 , wherein

the first hard mask formation film has a compressive stress greater than or equal to 0 Pa and equal to or less than 1000 MPa.

3. The method of claim 1 , wherein

the first hard mask formation film has a smaller crystal size than the second hard mask formation film.

4. The method of claim 1 , wherein

the second hard mask formation film has a higher compressive stress than the first hard mask formation film.

5. The method of claim 1 , wherein

the second hard mask formation film has a higher density than the first hard mask formation film.

6. The method of claim 1 , wherein

after the etching of the interlayer insulating film, the second hard mask is completely removed, or has a thickness equal to or less than 5 nm.

7. The method of claim 1 , wherein

a reflectivity of the first hard mask formation film is substantially equal to a reflectivity of the second hard mask formation film, and an attenuation coefficient of the first hard mask formation film is substantially equal to an attenuation coefficient of the second hard mask formation film.

8. The method of claim 1 , wherein

after the etching of the interlayer insulating film, an interconnect made of copper is formed in the interconnect groove.

9. The method of claim 1 , wherein

the etching of the interlayer insulating film includes forming the interconnect groove including at least three adjacent interconnect grooves between each adjacent pair of which a separation portion of the interlayer insulating film is interposed.

10. The method of claim 1 , wherein

the interlayer insulating film is made of a compound containing silicon.

11. The method of claim 10 , wherein

the interlayer insulating film includes a multilayer film of a silicon oxycarbide film having a relative dielectric constant of 2.5, and a silicon oxycarbide film having a relative dielectric constant of 3.0.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2014
From: HARADA, TAKESHI; HINOMURA, TORU; TORAZAWA, NAOKI; KABE, TATSUYA
To: PANASONIC CORPORATION
Reel/Frame 031990/0304 →