Locked loop circuits and methods
View Patent ↗The present invention provides a locked loop circuit in which the input clock signal is delayed according to a saw-tooth signal in order to output a range of frequencies not necessarily equal to an integer multiple of the input clock signal. The absolute value of the delay (i.e. the difference between the maximum and minimum values of the saw-tooth delay) can be calibrated by detecting the value of the circuit phase detector at the wrap point of the saw-tooth.
1. A locked loop circuit, comprising:
a delay cell for receiving a clock signal, applying a delay in accordance with a saw-tooth pattern and outputting a delayed clock signal;
a comparator for comparing the phase of the delayed clock signal and the phase of an output signal, and outputting a comparison signal;
an integrator for integrating the comparison signal and outputting an integrated signal;
an oscillator for generating the output signal as controlled by the integrated signal; and
feedback circuitry for measuring the comparison signal at a wrap point of the saw-tooth pattern and controlling the amplitude of the saw-tooth pattern in dependence on the measured comparison signal.
2. The locked loop circuit according to claim 1 , wherein the saw-tooth pattern comprises repeated cycles of sequentially incrementing or decrementing delay values followed by a wrap point.
3. The locked loop circuit according to claim 1 , wherein the delay is incremented for successive transitions of the clock signal between a minimum delay value and a maximum delay value followed by a wrap point to the minimum delay value, or decremented for successive transitions of the clock signal between a maximum delay value and a minimum delay value followed by a wrap point to the maximum delay value.
4. The locked loop circuit according to claim 3 , further comprising a controller for controlling the magnitude of the delay increment or decrement between successive transitions in order to control the frequency of the output signal relative to the frequency of the clock signal.
5. The locked loop circuit according to claim 4 , further comprising an input for receiving an input signal, wherein the controller is configured to control the magnitude of the delay increment or decrement in dependence on the input signal in order to modulate the output signal.
6. The locked loop circuit according to claim 3 , wherein the amplitude of the saw-tooth pattern corresponds to the difference between the minimum delay value and the maximum delay value.
7. The locked loop circuit according to claim 1 , wherein the feedback circuitry is configured to control the amplitude of the saw-tooth pattern so as to minimize the value of the comparison signal at the wrap point.
8. The locked loop circuit according to claim 7 , wherein the amplitude of the saw-tooth pattern is controlled so as to equal a period of the output signal.
9. The locked loop circuit according to claim 1 , further comprising a saw-tooth generator for generating a saw-tooth signal for controlling the delay cell.
10. The locked loop circuit according to claim 9 , further comprising a variable gain element for applying a variable gain to the saw-tooth signal, wherein the feedback circuitry is arranged to control the variable gain in dependence on the measured comparison signal.
11. The locked loop circuit according to claim 1 , wherein the servo loop comprises a gating element for gating the comparison signal at a wrap point of the saw-tooth pattern.
12. The locked loop circuit according to claim 11 , wherein the feedback circuitry further comprises:
an integrator for integrating the gated comparison signal; and
a comparator for comparing the integrated gated comparison signal with upper and lower thresholds, and increasing or decreasing the amplitude of the saw-tooth pattern in accordance with said comparison.