Stacked semiconductor package and method for manufacturing the same

1. A stacked semiconductor package comprising:

a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface;

a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and

a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.

2. The stacked semiconductor package according to claim 1 , wherein the molding part comprises:

a first molding part substantially covering the first surface of the first semiconductor chip and having the openings which expose the one end of the first through electrodes; and

a second molding part formed to substantially cover the fourth surface of the second semiconductor chip and side surfaces of the first and second semiconductor chips.

3. The stacked semiconductor package according to claim 1 , further comprising:

conductive connection members formed between the first through electrodes and the second through electrodes; and

an adhesive member formed between the first semiconductor chip and the second semiconductor chip.

4. The stacked semiconductor package according to claim 1 , further comprising:

anisotropic conductive material interposed between the first through electrodes and the second through electrodes and between the first semiconductor chip and the second semiconductor chip.

5. The stacked semiconductor package according to claim 1 , further comprising:

external connection terminals mounted to the one end of the first through electrodes which are exposed through the molding part.

6. The stacked semiconductor package according to claim 1 , further comprising:

redistribution lines formed over the molding part and electrically connected with the one end of the first through electrodes exposed through the molding part;

an insulation layer formed over the molding part including the redistribution lines and exposing portions of the redistribution lines; and

external connection terminals mounted to the portions of the redistribution lines exposed through the insulation layer.

7. The stacked semiconductor package according to claim 1 , further comprising:

a structural body having connection electrodes which are electrically connected with the one end of the first through electrodes exposed through the molding part.

8. The stacked semiconductor package according to claim 7 , further comprising:

conductive connection members electrically connecting the one end of the first through electrodes with the connection electrodes.

9. The stacked semiconductor package according to claim 7 , wherein the structural body comprises any one of a printed circuit board, an interposer, and a semiconductor package.