Semiconductor device
A first semiconductor device comprising: a first conductivity type drift region formed in a semiconductor substrate; a second conductivity type body region formed at an upper surface of the semiconductor substrate on an upper surface side of the drift region; a first conductivity type first semiconductor region formed on a part of an upper surface of the body region; and a trench gate type insulated gate penetrating the first semiconductor region and the body region, and formed to a depth at which the insulated gate contacts the drift region. A part of the insulated gate on a drift region side relative to the body region is deeper at a center portion than at both end portions in a longitudinal direction of the insulated gate.
1. A semiconductor device comprising:
a first conductivity type drift region formed in a semiconductor substrate;
a second conductivity type body region formed at an upper surface of the semiconductor substrate on an upper surface side of the drift region;
a first conductivity type first semiconductor region formed on a part of an upper surface of the body region; and
a trench gate type insulated gate penetrating the first semiconductor region and the body region, and formed to a depth at which the insulated gate contacts the drift region, wherein
a part of the insulated gate on a drift region side relative to the body region becomes gradually deeper at a center portion than at a from both end portions to a center portion in a longitudinal direction of the insulated gate, and
a bottom portion of the insulated gate has an arc-like pattern, wherein a trench width of the center portion of the insulated gate becomes wider than a trench width of each of the both end portions to the center portion of the insulated gate in a plan view of the semiconductor substrate.
2. The semiconductor device according to claim 1 , further comprising:
a bypass portion in which the first semiconductor region is not formed, the bypass portion being formed on at least a part of a surface of the semiconductor substrate opposing the center portion in the longitudinal direction of the insulated gate.