IP Library Granted Patent US 9,178,464
Granted Patent B2
US 9,178,464 · App. 13/699,810 · Granted Nov 3, 2015

Method and system for motor speed control

Inventors: James Aweya (Abu Dhabi, AE); Nayef AlSindi (Abu Dhabi, AE)
Assignees: British Telecommunications plc; Khalifa University of Science, Technology and Research; Emirates Telecommunications Corporation
H02P29/0005H02P5/46H02P23/0068H02P5/74
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Quick Facts
Patent No.
US 9,178,464
App. No.
13/699,810
Granted
Nov 3, 2015
Kind
B2
Abstract

This invention relates to methods and devices for motor speed control. The invention has particular application in the control of motors over packet networks. In embodiments of the invention, phase-locked loop principles are used to remotely control the speed of an electric motor over a packet network. The setpoint for the motor is supplied by arriving timestamps from a speed-mapped variable frequency source. The shaft speed of the motor is measured with a tachometer with its output proportional to the motor speed. Any deviation of the actual speed from the setpoint is amplified by the power amplifier whose output drives the motor. Speed control over packet networks allow smoother operation of a process, acceleration control, different operating speeds for each process recipe, compensation for changing process variables, slow operation for setup purposes, adjustments to the rate of production, accurate positioning, and control torque or tension of a system.

Claims (47)

1. A system for controlling the speed of a motor, the system including:

the motor; and

an analogous phase locked loop connected to a network and arranged to receive a timing signal from that network and to control the speed of the motor according to that timing signal,

wherein the analogous phase locked loop is arranged to generate an error signal which is the difference between the timing signal received from the network and a counter signal from a counter which is incremented according to the speed of the motor, and to adjust the speed of the motor according to the error signal.

2. A system according to claim 1 , wherein the analogous phase locked loop includes:

a speed encoder arranged to detect the speed of the motor and convert it to a sequence of pulses encoding the speed of the motor;

a local counter which is incremented by pulses from the speed encoder and is arranged to output the counter signal;

a receiver connected to the network and arranged to receive a timing signal from the network; and

a phase detector arranged to determine the error signal based on the difference between said counter signal and said timing signal.

3. A system according to claim 2 , wherein the analogous phase locked loop further includes a loop filter arranged to remove possible noise in the error signal.

4. A system according to claim 2 , wherein the analogous phase locked loop further includes an amplifier which amplifies the error signal before passing it to the motor.

5. A system according to claim 2 , wherein the timing signal is a sequence of timestamps.

6. A system according to claim 2 , wherein the speed encoder is an optical tachometer.

7. A system according to claim 1 , wherein the network is a packet network.

8. A system for remotely controlling the speed of the motor, the system including:

a central control unit, a motor control unit and a network connecting the control units, wherein:

the central control unit includes:

a variable frequency transmitter, arranged to send a timing signal over the network which represents the desired speed of the motor; and

the motor control unit includes:

the motor; and

an analogous phase locked loop connected to a network and arranged to receive a timing signal from that network and to control the speed of the motor according to that timing signal,

wherein the analogous phase locked loop is arranged to generate an error signal which is the difference between the timing signal received from the network and an output signal of a counter which is incremented according to the speed of the motor, and to adjust the speed of the motor according to the error signal.

9. A system according to claim 8 , wherein the analogous phase locked loop includes:

a speed encoder arranged to detect the speed of the motor and convert it to a sequence of pulses encoding the speed of the motor;

a local counter arranged to output a counter signal which is incremented by pulses from the speed encoder;

a receiver connected to a network and arranged to receive a timing signal from that network; and

a phase detector arranged to determine the error signal based on the difference between said counter signal and said timing signal.

10. A system according to claim 8 , wherein the analogous phase locked loop further includes a loop filter arranged to remove possible noise in the error signal.

11. A system according to claim 8 , wherein the analogous phase locked loop further includes an amplifier which amplifies the error signal before passing it to the motor.

12. A system according to claim 8 , wherein the timing signal is a sequence of timestamps.

13. A system according to claim 8 , wherein the speed encoder is an optical tachometer.

14. A system according to claim 8 , wherein the network is a packet network.

15. A system according to claim 8 , wherein there are a plurality of said motor control units and the central control unit sends timing signals to each of said plurality of motor control units so as to cause the motors of the motor control units to operate in synchronization with each other.

16. A system according to claim 15 , wherein the timing signals are multicast from the central control unit to each of said plurality of motor control units.

17. A system according to claim 8 , wherein the central control unit includes:

an oscillator generating a variable frequency pulsed signal; and a speed counter which counts the pulses from the oscillator, wherein the timing signals are samples of the output of the speed counter.

18. A method of remotely controlling the speed of a motor, the motor forming part of an analogous phase-locked loop, the method including the steps of:

sending, over a network, a timing signal which represents desired speed of the motor to the analogous phase-locked loop;

detecting the speed of the motor as a local oscillator signal;

receiving said timing signal;

comparing the phase of said timing signal and said oscillator signal to generate an error signal; and

adjusting the speed of the motor according to the error signal.

19. A method according to claim 18 , wherein there are a plurality of said motors and the method includes the steps of sends timing signals over said network to each of said plurality of motors so as to cause the motors to operate in synchronization with each other.

20. A method according to claim 18 , wherein the timing signals are multicast over the network to each of said plurality of motors.

21. A method according to claim 18 , wherein, on start-up, said motor is initially free-running, and further comprising the steps of:

receiving the first timing signal from the network and using it to initialize a local counter of the analogous phase-locked loop which counts pulses of the local oscillator signal, and

starting the steps of detecting, receiving, comparing and adjusting after receipt of said first timing signal.

Assignments (2)
CHANGE OF NAME Recorded Aug 8, 2019
From: KHALIFA UNIVERSITY OF SCIENCE, TECHNOLOGY AND RESEARCH
To: KHALIFA UNIVERSITY OF SCIENCE AND TECHNOLOGY
Reel/Frame 050006/0773 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2013
From: AWEYA, JAMES; AL SINDI, NAYEF
To: KHALIFA UNIVERSITY OF SCIENCE, TECHNOLOGY, AND RESEARCH; BRITISH TELECOMMUNICATIONS PLC; EMIRATES TELECOMMUNICATIONS CORPORATION
Reel/Frame 031468/0703 →
Continuity (1)
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