System and method for high-performance, low-power data center interconnect fabric
A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.
1. A computing system, comprising:
at least one server on a chip including one or more processing cores, a plurality of peripheral interfaces, a plurality of interconnect portions and an interconnect portion selector, wherein the interconnect portion selector is coupled to each one of the plurality of peripheral interfaces and to each one of the plurality of interconnect portions, wherein the interconnect portions each enable the computing system to be communicatively connected to a plurality of other computing systems, wherein a first one of the interconnect portions supports single-node operation by the server on a chip, wherein a first set of the interconnect portions support multi-node operation by the server on a chip, and wherein the interconnect portion selector enables data communication of each one of the peripheral interfaces to be selectively steered to the first one of the interconnect portions and to the first set of the interconnect portions;
operating system software accessible by each one of the one or more processing cores of the at least one server on a chip; and
a first memory structure coupled to at least one direct memory access portion of the at least one server on a chip for providing direct access memory functionality within the computing system.
2. The computing system of claim 1 , further comprising:
a second memory structure coupled to at least one of the peripheral interfaces for providing persistent storage functionality within the computing system.
3. The computing system of claim 1 wherein the plurality of peripheral interfaces includes:
a PCIe interface; and
a SATA interface.
4. The computing system of claim 1 wherein: first memory structure includes double data rate (DDR) random access memory (RAM)
each one of the interconnect portions includes a respective one of a plurality of combo PHYs; and
the interconnect portion selector is a peripheral interface-to-combo PHY selector.
5. The computing system of claim 4 wherein the plurality of peripheral interfaces includes:
a PCIe interface; and
a SATA interface.
6. A computing system, comprising:
at least one server on a chip including one or more processing cores, a plurality of peripheral interfaces, a plurality of interconnect portions, an Ethernet media access control (MAC), a first interconnect portion selector and a second interconnect portion selector, wherein the first interconnect portion selector is coupled between the plurality of peripheral interfaces and the interconnect portions, wherein the second interconnect portion selector is coupled between the Ethernet MAC and the interconnect portions, wherein the interconnect portions enable the computing system to be communicatively connected to a plurality of other computing systems, wherein a first one of the interconnect portions supports single-node operation by the server on a chip, wherein a first set of the interconnect portions support multi-node operation by the server on a chip, wherein the first interconnect portion selector enables data communication of each one of the peripheral interfaces to be selectively steered to the first one of the interconnect portions and to the first set of the interconnect portions, and wherein the second interconnect portion selector enables data communication of the Ethernet MAC to be selectively steered to the first one of the interconnect portions and to the set of the interconnect portions;
operating system software accessible by each one of the one or more processing cores of the at least one server on a chip; and
a first memory structure coupled to at least one direct memory access portion of the at least one server on a chip for providing direct access memory functionality within the computing system.
7. The computing system of claim 6 , further comprising:
a second memory structure coupled to at least one of the peripheral interface for providing persistent storage functionality within the computing system.
8. The computing system of claim 6 wherein the plurality of peripheral interfaces includes:
a PCIe interface; and
a SATA interface.
9. The computing system of claim 6 wherein:
each one of the interconnect portions includes a respective one of a plurality of combo PHYs;
the first interconnect portion selector is a peripheral interface-to-combo PHY selector; and
the second interconnect portion selector is a structure configured for muxing connections between the Ethernet MAC and the interconnect portions.
10. The computing system of claim 9 wherein the plurality of peripheral interfaces includes:
a PCIe interface; and
a SATA interface.
11. A computing system, comprising:
a server on a chip including one or more processing cores, a plurality of peripheral interfaces, a plurality of interconnect portions, an Ethernet media access control (MAC), and an interconnect portion selector, wherein the interconnect portion selector is coupled between the interconnect portions and at least one of the plurality of peripheral interfaces and the Ethernet MAC, wherein the interconnect portions enable the computing system to be communicatively connected to a plurality of other computing systems, wherein a first one of the interconnect portions supports single-node operation by the server on a chip, wherein a first set of the interconnect portions support multi-node operation by the server on a chip, and wherein the interconnect portion selector enables data communication of at least one of the Ethernet MAC and the plurality of peripheral interfaces to be selectively steered to the first one of the interconnect portions and to the first set of the interconnect portions; and
operating system software accessible by each one of the one or more processing cores of the server on a chip.
12. The computing system of claim 11 wherein:
the interconnect portion selector is coupled to the plurality of interconnect portions and to the Ethernet MAC; and
the interconnect portion selector enables data communication of the Ethernet MAC to be selectively steered to the first one of the interconnect portions and to the first set of the interconnect portions.
13. The computing system of claim 11 wherein:
the interconnect portion selector is coupled to the interconnect portions and to the peripheral interfaces; and
the interconnect portion selector enables data communication of each one of the peripheral interfaces to be selectively steered to the first one of the interconnect portions and to the first set of the interconnect portions.
14. The computing system of claim 11 wherein:
each one of the interconnect portions includes a respective one of a plurality of combo PHYs; and
the interconnect portion selector is a structure configured for muxing connections between the Ethernet MAC and the interconnect portions.
15. The computing system of claim 14 wherein the plurality of peripheral interfaces includes:
a PCIe interface; and
a SATA interface.
16. The computing system of claim 15 wherein:
the interconnect portion selector is coupled to the plurality of interconnect portions and to the Ethernet MAC; and
the interconnect portion selector enables data communication of the Ethernet MAC to be selectively steered to the first one of the interconnect portions and to the first set of the interconnect portions.
17. The computing system of claim 15 wherein:
the interconnect portion selector is coupled to the interconnect portions and to the peripheral interfaces; and
the interconnect portion selector enables data communication of each one of the peripheral interfaces to be selectively steered to the first one of the interconnect portions and to the first set of the interconnect portions.