System and Method for High-Performance, Low-Power Data Center Interconnect Fabric
A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.
1 . A system on a chip, comprising:
one or more processing cores;
one or more management processors coupled to each one of the one or more processing cores;
one or more communication interfaces; and
one or more interrupt controllers coupled between each one of the one or more processing cores and the one or more management processors for enabling an interrupt transmitted for reception by a first one of the one or more processing cores to be reflected to the one or more management processors from the first one of the one or more processing cores while the first one of the one or more processing cores is in the inactive state.
2 . The system on a chip of claim 1 , further comprising:
a switching fabric coupled between the one or more processing cores, the one or more management processors and the one or more communication interfaces, wherein the one or more interrupt controllers coupled to the switching fabric for enabling the interrupt transmitted for reception by at least one of the one or more processing cores to be reflected to the one or more management processors from the first one of the one or more processing cores while the first one of the one or more processing cores is in the inactive state.
3 . The system on a chip of claim I wherein the one or more management processors cause the interrupt to be provided to the first one of the one or more processing cores in response to the first one of the one or more processing cores being transitioned from the inactive state to an active state.
4 . The system on a chip of claim 3 wherein:
the interrupt is maintained by the one or more management processors until the first one of the one or more processing cores being transitioned from the inactive state to the active state; and
the interrupt is handled directly by the one or more interrupt controllers in response to the first one of the one or more processing cores being transitioned from the inactive state to the active state.
5 . The system on a chip of claim 1 wherein:
the one or more management processors cause the interrupt directed to the first one of the one or more processing cores to be held in the switching fabric while the first one of the one or more processing cores is in the inactive state;
the one or more management processors assess the one or more processing cores to determine a second one of the one or more processing cores that is currently in an active state; and
the one or more management processors cause the communication request to be delivered to the second one of the one or more processing cores for allowing the second one of the one or more processing cores to perform the task initiated by the communication request after determining that the second one of the one or more processing cores is currently in the active state.
6 . The system on a chip of claim 5 wherein:
the one or more management processors assess the second one of the one or more processing cores to determine an available processing power capacity prior to causes the communication request to be delivered to the second one of the one or more processing cores; and
the one or more management processors cause the communication request to be delivered to the second one of the one or more processing cores in response to determining that the second one of the one or more processing cores has sufficient processing power available for performing the task to be initiated by the communication request.
7 . A computing system, comprising:
one or more server on a chip units each having one or more processing cores and one or more power management portions coupled between each one of the one or more processing cores one or more processing cores;
one or more interconnect portions couple to each one of the one or more server on a chip units for enabling the computing system to be communicatively connected to one or more other computing systems; and
one or more interrupt controllers coupled between each one of the one or more processing cores and the one or more power management portions for enabling an interrupt transmitted for reception by a first one of the one or more processing cores to be reflected to the one or more management processors from the first one of the one or more processing cores while the first one of the one or more processing cores is in the inactive state,
8 . The computing system of claim 7 wherein:
the one or more server on a chip units each include a switching fabric coupled between the one or more processing cores, the power management portions and the one or more communication interfaces thereof, and
the one or more interrupt controllers are coupled to the switching fabric for enabling the interrupt transmitted for reception by at least one of the one or more processing cores to be reflected to the one or more management processors from the first one of the one or more processing cores while the first one of the one or more processing cores is in the inactive state.
9 . The computing system of claim 7 wherein the one or more power management portions cause the interrupt to be provided to the first one of the one or more processing cores in response to the first one of the one or more processing cores being transitioned from the inactive state to an active state.
10 . The computing system of claim 9 wherein:
the interrupt is maintained by the one or more power management portions until the first one of the one or more processing cores being transitioned from the inactive state to the active state; and
the interrupt is handled directly by the one or more interrupt controllers in response to the first one of the one or more processing cores being transitioned from the inactive state to the active state.
11 . The computing system of claim 7 wherein:
the one or more power management portion cause the interrupt directed to the first one of the one or more processing cores to be held in the switching fabric while the first one of the one or more processing cores is in the inactive state;
the one or more power management portion assess the one or more processing cores to determine a second one of the one or more processing cores that is currently in an active state; and
the one or more power management portion cause the communication request to be delivered to the second one of the one or more processing cores for allowing the second one of the one or more processing cores to perform the task initiated by the communication request after determining that the second one of the one or more processing cores is currently in the active state.
12 . The computing system of claim 11 wherein:
the one or more management processors assess the second one of the one or more processing cores to determine an available processing power capacity prior to causes the communication request to be delivered to the second one of the one or more processing cores; and
the one or more management processors cause the communication request to be delivered to the second one of the one or more processing cores in response to determining that the second one of the one or more processing cores has sufficient processing power available for performing the task to be initiated by the communication request.
13 . A computing system, comprising:
one or more server on a chip units each having one or more processing cores and one or more power management portions coupled between each one of the one or more processing cores one or more processing cores;
one or more interconnect portions couple to each one of the one or more server on a chip units for enabling the computing system to be communicatively connected to one or more other computing systems;
one or more interrupt controllers coupled between each one of the one or more processing cores and the one or more power management portions for enabling an interrupt transmitted for reception by a first one of the one or more processing cores to be reflected to the one or more management processors from the first one of the one or more processing cores while the first one of the one or more processing cores is in the inactive state
operating system software accessible by each one of the one or more processing cores of the one or more server on a chip units; and
a first memory structure coupled to one or more direct memory access portions of each one of the one or more server on a chip units for providing direct access memory functionality within the computing system.
14 . The computing system of claim 13 wherein:
the one or more server on a chip units each include a switching fabric coupled between the one or more processing cores, the power management portions and the one or more communication interfaces thereof; and
the one or more interrupt controllers are coupled to the switching fabric for enabling the interrupt transmitted for reception by at least one of the one or more processing cores to be reflected to the one or more management processors from the first one of the one or more processing cores while the first one of the one or more processing cores is in the inactive state.
15 . The computing system of claim 13 wherein the one or more power management portions cause the interrupt to be provided to the first one of the one or more processing cores in response to the first one of the one or more processing cores being transitioned from the inactive state to an active state.
16 . The computing system of claim 15 wherein:
the interrupt is maintained by the one or more power management portions until the first one of the one or more processing cores being transitioned from the inactive state to the active state; and
the interrupt is handled directly by the one or more interrupt controllers in response to the first one of the one or more processing cores being transitioned from the inactive state to the active state,
17 . The computing system of claim 13 wherein:
the one or more power management portion cause the interrupt directed to the first one of the one or more processing cores to be held in the switching fabric while the first one of the one or more processing cores is in the inactive state;
the one or more power management portion assess the one or more processing cores to determine a second one of the one or more processing cores that is currently in an active state; and
the one or more power management portion cause the communication request to be delivered to the second one of the one or more processing cores for allowing the second one of the one or more processing cores to perform the task initiated by the communication request after determining that the second one of the one or more processing cores is currently in the active state.
18 . The computing system of claim 17 wherein:
the one or more management processors assess the second one of the one or more processing cores to determine an available processing power capacity prior to causes the communication request to be delivered to the second one of the one or more processing cores; and
the one or more management processors cause the communication request to be delivered to the second one of the one or more processing cores in response to determining that the second one of the one or more processing cores has sufficient processing power available for performing the task to be initiated by the communication request.
19 . The computing system of claim 13 , further comprising:
a second memory structure coupled to one or more memory interfaces of each one of the one or more server on a chip units for providing persistent storage functionality within the computing system.
20 . The computing system of claim 19 wherein the one or more memory interfaces of the one or more server on a chip units includes at least one of:
a NAND flash interface;
a eMMC interface;
a PCIe interface;
a SATA interface;
a SD interface; and
a SAS interface.
21 . The computing system of claim 19 wherein the one or more memory interfaces of the one or more server on a chip units includes:
a eMMC interface;
a PCIe interface;
a SATA interface;
a SD interface; and
a SAS interface.