Protecting secure software in a multi-security-CPU system

1. A computing system, comprising:

a first central processing unit (CPU);

a second CPU in communication with the first CPU and with a host processor;

a memory;

an instruction checker circuitry,

where, in response to a request by the host processor to boot the second CPU,

the second CPU is configured to execute a two-stage secure booting,

where the second CPU is configured to:

execute first stage code to request, from the first CPU, decryption information to decrypt a second stage code of the two-stage secure booting;

decrypt the second stage code stored in a first region of the memory;

write the decrypted second stage code to a second region of the memory; and

execute the second stage code of the two-stage secure booting, and

where, the instruction checker circuitry is configured to monitor execution of the second stage code by the second CPU, and in response to detection of an attempt to execute an instruction located outside of the second region of the memory, prevent execution of the instruction by the second CPU.

2. The computing system of claim 1 , where the host processor is configured to write encrypted code, including the first stage code and the second stage code, for executing the two-stage secure booting into the memory.

3. The computing system of claim 2 , where the the first and second CPUs are located on a system on a chip (SOC), and where a boot loader circuitry is configured to:

read the first stage code from the memory;

decrypt the first stage code on the SOC; and

write the decrypted first stage code into a local memory accessible by the second CPU.

4. The computing system of claim 3 , where the first CPU is further configured to:

authenticate the decrypted first stage code for execution by the second CPU; and

authorize the second CPU to execute the decrypted first stage code from the memory accessible by the second CPU.

5. The computing system of claim 3 , where the decrypted first stage code is executable to make decisions regarding how to load, decrypt and execute the second stage code.

6. The computing system of claim 3 , where in executing the decrypted first stage code, the second CPU is configured to request the first CPU to generate a key usable to decrypt the second stage code, in response to which the first CPU is further configured to:

generate the key with specified access rights for use by the second CPU, the access rights including a first region of the memory from which to decrypt the second stage code, and a second region of the memory to which to write the decrypted second stage code; and

aid the second CPU to configure a memory checker to ensure that the second CPU occurs only decrypts the second stage code from the first region and that the second CPU only writes the decrypted second stage code to the second region of the memory.

7. The computing system of claim 6 , where the first region of the memory is accessible by the host processor and the second region of the memory is inaccessible by the host processor.

8. The computing system of claim 1 , where the instruction checker circuitry is configured to:

monitor execution of instructions of the decrypted second stage code by the second CPU; and

prevent execution of the instruction that is located outside of the second region of the memory, and force execution of another instruction that is located within the second region of the memory.

9. The computing system of claim 8 , where the instruction checker circuitry is further configured to reset the computing system in response to detection of the attempt to execute the instruction located outside of the second region of the memory.

10. The computing system of claim 1 , where the first CPU operates at a first security level and the second CPU operates at a second security level less secure than the first security level.

11. A method for securing software in a multi-security central processing unit (CPU) system that includes a first and a second CPU communicatively coupled together, comprising:

receiving a request from a host processor to boot the second CPU;

decrypting, by a first stage boot loader circuitry, an encrypted first stage code and writing decrypted first stage code into a memory accessible by the second CPU;

executing, by the second CPU, the decrypted first stage code, where the executing comprises:

decrypting an encrypted second stage code from the memory; and

writing the decrypted second stage code at a designated region of the memory;

monitoring, by an instruction checker, an address of an instruction being executed by the second CPU during execution of the decrypted second stage code; and

alerting the second CPU, by the instruction checker, in response to the address of the instruction being executed by the second CPU being outside of the designated region.

12. The method of claim 11 , further comprising:

reading, by the first stage boot loader of the host processor, the first stage code from the memory;

authenticating, by the first CPU, the decrypted first stage code for execution by the second CPU; and

authorizing, by the first CPU, the second CPU to execute the decrypted first stage code from the memory accessible by the second CPU.

13. The method of claim 12 , further comprising:

requesting, by the second CPU, that the first CPU generate a key for decrypting the second stage code stored in a first region of the memory;

generating the key by the first CPU, the key including access rights to the first region of the memory from which to decrypt the second stage code and the designated region of the memory to which to write the decrypted second stage code; and

creating, by the first and second CPUs, a memory checker.

14. The method of claim 13 , further comprising:

monitoring, by the memory checker, decryption of the encrypted second stage code attempted by the host processor;

determining, by the memory checker, whether decryption is from the first region to the designated region; and

in response to determining that decryption is attempted from other than the first region or to other than the designated region, alerting, by the memory checker, the second CPU of a decryption violation.

15. The method of claim 14 , further comprising:

preventing, by the second CPU, the decryption of the encrypted second stage code or forcing the decrypted second stage code to be written to the designated region.

16. A computing system, comprising:

a first central processing unit (CPU);

a dynamic random access memory (DRAM) communicatively connected with the first CPU;

a flash memory;

a second CPU communicatively coupled with the first CPU and with the DRAM;

a host processor coupled with the first and second CPUs, with the DRAM and with the flash memory, the host processor configured to write encrypted code into the DRAM from the flash memory, the encrypted code including a first stage code and a second stage code for executing a two-stage boot process;

where the first CPU is configured to:

receive a request from the host processor to boot the second CPU;

in response to the request, decrypt the first stage code; and

write the decrypted first stage code into a memory region accessible by the second CPU;

where the second CPU is configured to execute the decrypted first stage code stored in the memory region accessible by the second CPU to:

decrypt the encrypted second stage code stored in a first region of the DRAM; and

write the decrypted second stage code into a second region of the DRAM; and

execute the decrypted second stage code from the second region of the DRAM; and

where a memory checker is configured to:

monitor that the encrypted second stage code is being read from within the first region of the DRAM and that the decrypted second stage code is being written within the second region of the DRAM by the second CPU; and

in response to the second CPU accessing DRAM outside of the first region and the second region, abandon the decryption of the encrypted second stage code

such that the host processor cannot access either the decrypted first stage code or the decrypted second stage code after decryption.

17. The computing system of claim 16 , further comprising a first stage boot loader executable to read the first stage code from DRAM, where the memory region accessible by the second CPU comprises a private local memory of the second CPU, and where the first CPU is further configured to:

authenticate the decrypted first stage code for execution by the second CPU; and

authorize the second CPU to execute the decrypted first stage code from the private local memory.

18. The computing system of claim 17 , where the second CPU is further configured to request the first CPU to generate a key, in response to which the first CPU is further configured to generate the key including access rights comprising the first region of the DRAM from which to decrypt the second stage code and the second region of the DRAM to which to write the decrypted second stage code.

19. The computing system of claim 18 , where the memory checker is configured to:

in response to the determination that decryption is attempted from other than the first region or the decrypted second stage code is being written to other than the second region, force the decrypted second stage code to be written to the second region.

20. A computing system, comprising:

a first central processing unit (CPU); and

a second CPU in communication with the first CPU and with a host processor,

where, in response to a request by the host processor to boot the second CPU, the first CPU is configured to boot the second CPU, where the boot comprises:

decryption of encrypted code to generate decrypted code; and

storage of the decrypted code within a designated region of a memory,

where the designated region is accessible by the second CPU but is inaccessible by the host processor; and

where an instruction checker is configured to:

monitor execution of the decrypted code from within the designated region by the second CPU; and

in response to detection of an attempt to execute an instruction located outside of the designated region of the memory, prevent execution of the instruction by the second CPU.