Data and key separation using a secure central processing unit

1. A computing system, comprising:

a first central processing unit (CPU); and

a second CPU coupled with the first CPU and with a host processor, where the second CPU and the host processor both request the first CPU to generate keys that have access rights to regions of memory to access specific data, and

where the first CPU is configured to, in response to a request from the second CPU, generate a unique key with a unique access right to a region of memory, the unique key usable only by the second CPU, not the host processor,

where the first CPU further comprises a variant module configured to provide a variant for the generation of the unique key, and

where the first CPU further comprises a filter module configured to filter requests coming from the host processor and the second CPU and to deny the host processor access to the variant module of the first CPU.

2. The computing system of claim 1 , where the first CPU is configured to deny the host processor from generating or using the unique key, where the first CPU operates at a first security level and the second CPU operates at a second security level less secure than the first security level.

3. The computing system of claim 1 , where the specific data being protected by the unique key comprises third-party digital content comprising audio, video or a combination thereof; and where the access right includes writing the content to a second region of memory.

4. The computing system of clam claim 1 , further comprising a first communication bus coupled between the host processor and the first CPU and a second communication bus coupled between the second CPU and the first CPU, the first communication bus being isolated from the second communication bus.

5. The computing system of claim 1 , where the key is usable by unsecure software executed by the host processor wanting access to or decryption of the specific data that is secured from access in the memory.

6. The computing system of claim 1 , where the filter module is configured to distinguish between requests from the host processor and the second CPU, respectively.

7. The computing system of claim 1 , where the first CPU further comprises a key generator, and the variant module is configured to provide the variant to an algorithm used by the key generator to generate the unique key for exclusive use by the second CPU.

8. The computing system of claim 7 , where the variant module constrains the variant to predetermined variants authorized for selection by the second CPU.

9. The computing system of claim 1 , where the unique key comprises a root key usable to decrypt a system or software file for execution by the computing system, where the host processor cannot generate or use the unique key.

10. The computing system of claim 1 , where the unique key is a first key, and where the first CPU is further configured to generate a second key that is usable by the host processor to access corresponding regions of memory to access specific data.

11. A method for data and key separation in a system on a chip (SOC), comprising:

receiving, by a first central processing unit (CPU), a request to generate a key from both a second central processing unit (CPU) and a host processor, the key including access rights to regions of memory to access specific data;

generating a first key, by the first CPU, for use by the host processor; and

generating a second key by the first CPU for use by the second CPU, where the second key is generated using a variant module and the second key includes a unique access right to a region of memory; and

denying, by the first CPU, the host processor from using the second key.

12. The method of claim 11 , further comprising:

receiving a subsequent request from the host processor to generate a key; and

determining, by a filter of the first CPU, whether the subsequent request from the host processor attempts generation of the second key.

13. The method of claim 11 , where generating the second key comprises:

receiving selection of an algorithm variant by the second CPU;

applying the algorithm variant to a key generator of the first CPU to generate the second key; and

providing access or decryption rights to only the second CPU corresponding to the second key.

14. The method of claim 13 , further comprising:

restricting the algorithm variant to one of multiple algorithm variants made available by the first CPU.

15. The method of claim 11 , further comprising:

detecting, by a filter module of the first CPU, access requests to the memory by the host processor and the second CPU; and

denying, by the filter module, access attempts by the host processor to the region in memory.

16. The method of claim 11 , where the second key further comprises a root key usable to decrypt a system or software file for execution by the system, where the host processor cannot generate or use the second key.

17. A computing system, comprising:

a first central processing unit (CPU); and

a second CPU coupled with the first CPU and with a host processor, where the second CPU and the host processor both request the first CPU to generate keys that have access rights to regions of memory to access specific data,

where the first CPU is configured to, in response to a request from the second CPU, generate a unique key using a variant module, the unique key comprising a root key usable to decrypt a system or software file for execution by the computing system, where the host processor cannot use the unique key, and

where the first CPU is further configured to, in response to a request from the host processor, generate a second key usable by the host processor.

18. The computing system of claim 17 , where the first CPU is further configured to write the system or software file to a protected region of memory inaccessible by the host processor from where the system or software file is executed by the computing system, where the first CPU operates at a first security level and the second CPU operates at a second security level less secure than the first security level.

19. The computing system of claim 17 , further comprising a first communication bus coupled between the host processor and the first CPU and a second communication bus coupled between the second CPU and the first CPU, the first communication bus being isolated from the second communication bus.

20. The computing system of claim 17 , where, the variant module is configured to provide a variant to an algorithm used to generate the unique key for exclusive use by the second CPU; and where the first CPU further comprises a filter module to filter requests coming from the host processor and the second CPU and to ensure that the second CPU has access to the variant module and that the host processor does not have access to the variant module.