Using a virtual to physical map for direct user space communication with a data storage device
View Patent ↗A data storage device includes multiple flash memory devices, where each of the flash memory devices are arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller that is operationally coupled with the flash memory devices. The memory controller is configured to receive a virtual to physical memory address translation map from a host device, where a physical memory address includes a physical address for memory on the host device. The memory controller is configured to store the virtual to physical memory address translation map in a memory module on the memory controller, receive commands directly from an application running on the host device, where the commands include virtual memory addresses that refer to the memory on the host device and translate the virtual memory addresses to physical memory addresses using the virtual to physical memory address translation map.
1. A data storage device, comprising:
a plurality of flash memory devices, each of the flash memory devices being arranged into a plurality of blocks having a plurality of pages for storing data; and
a memory controller operationally coupled with the flash memory devices, the memory controller being configured to:
receive a virtual to physical memory address translation map from a host device, wherein a physical memory address includes a physical address for memory on the host device;
store the virtual to physical memory address translation map in a memory module on the memory controller;
receive commands directly from an application running on the host device such that the commands bypass a driver and a kernel on the host device, wherein the commands include virtual memory addresses that refer to the memory on the host device; and
translate the virtual memory addresses to physical memory addresses using the virtual to physical memory address translation map.
2. The data storage device of claim 1 wherein the memory controller is configured to receive commands directly from the application running on the host device through one of a plurality of queues.
3. The data storage device of claim 2 wherein the virtual to physical memory address translation map is shared among the plurality of queues.
4. The data storage device of claim 3 wherein the commands include virtual memory addresses with an offset.
5. The data storage device of claim 2 wherein the memory controller is configured to receive a plurality of virtual to physical memory address translation maps from the host device, wherein each of the virtual to physical memory address translation maps corresponds to one of the plurality of queues and the commands include virtual memory addresses with an offset.
6. The data storage device of claim 2 wherein the memory controller is configured to receive a plurality of virtual to physical memory address translation maps from the host device, wherein the virtual to physical memory address translation maps are shared among the plurality of queues and the commands include virtual memory addresses with an offset.
7. The data storage device of claim 1 wherein the memory module on the memory controller includes a dynamic random access memory (DRAM) and the memory controller includes a memory address translator, wherein the memory address translator is configured to translate the virtual memory addresses to physical memory addresses using the virtual to physical memory address translation map stored in the DRAM.
8. A method comprising:
receiving, at a memory controller, a virtual to physical memory address translation map from a host device, wherein a physical memory address includes a physical address for memory on the host device;
storing the virtual to physical memory address translation map in a memory module on the memory controller;
receiving commands directly from an application running on the host device such that the commands bypass a driver and a kernel on the host device, wherein the commands include virtual memory addresses that refer to the memory on the host device; and
translating the virtual memory addresses to physical memory addresses using the virtual to physical memory address translation map.
9. The method of claim 8 wherein receiving the commands includes receiving the commands directly from the application running on the host device through one of a plurality of queues.
10. The method of claim 9 further comprising sharing the virtual to physical memory address translation map among the plurality of queues.
11. The method of claim 10 the commands include virtual memory addresses with an offset.
12. The method of claim 9 wherein:
receiving the virtual to physical memory address translation map from a host device includes receiving a plurality of virtual to physical memory address translation maps from the host device,
each of the virtual to physical memory address translation maps corresponds to one of the plurality of queues, and
the commands include virtual memory addresses with an offset.
13. The method of claim 9 wherein:
receiving the virtual to physical memory address translation map from a host device includes receiving a plurality of virtual to physical memory address translation maps from the host device,
the virtual to physical memory address translation maps are shared among the plurality of queues, and
the commands include virtual memory addresses with an offset.
14. A system comprising:
a host device configured to generate a virtual to physical memory address translation map, the host device including memory, a driver, a kernel and at least one application running on the host; and
a data storage device operationally coupled with the host device, the data storage device comprising:
a plurality of flash memory devices, each of the flash memory devices being arranged into a plurality of blocks having a plurality of pages for storing data; and
a memory controller operationally coupled with the flash memory devices, the memory controller being configured to:
receive the virtual to physical memory address translation map from the host device, wherein a physical memory address includes a physical address for the memory on the host device;
store the virtual to physical memory address translation map in a memory module on the memory controller;
receive commands directly from the at least one application running on the host device such that the commands bypass the driver and the kernel on the host device, wherein the commands include virtual memory addresses that refer to the memory on the host device; and
translate the virtual memory addresses to physical memory addresses using the virtual to physical memory address translation map.
15. The system of claim 14 wherein:
the host device includes a plurality of queues; and
the memory controller is configured to receive commands directly from the application running on the host device through one of the plurality of queues.
16. The system of claim 15 wherein the virtual to physical memory address translation map is shared among the plurality of queues.
17. The system of claim 16 wherein the commands include virtual memory addresses with an offset.
18. The system of claim 15 wherein:
the host device is configured to generate a plurality of virtual to physical memory address translation maps; and
the memory controller is configured to receive the plurality of virtual to physical memory address translation maps from the host device, wherein each of the virtual to physical memory address translation maps corresponds to one of the plurality of queues and the commands include virtual memory addresses with an offset.
19. The system of claim 15 wherein:
the host device is configured to generate a plurality of virtual to physical memory address translation maps; and
the memory controller is configured to receive the plurality of virtual to physical memory address translation maps from the host device, wherein the virtual to physical memory address translation maps are shared among the plurality of queues and the commands include virtual memory addresses with an offset.
20. The system of claim 14 wherein the memory module on the memory controller includes a dynamic random access memory (DRAM) and the memory controller includes a memory address translator, wherein the memory address translator is configured to translate the virtual memory addresses to physical memory addresses using the virtual to physical memory address translation map stored in the DRAM.