Semiconductor device and method for fabricating the same
A vertical channel transistor includes a pillar formed over a substrate, and a gate electrode formed on sidewalls of the pillar, wherein the pillar includes a source area, a vertical channel area over the source area, a drain area over the vertical channel area, and a leakage prevention area interposed between the vertical channel area and the drain area.
1. A vertical channel transistor comprising:
a pillar formed over a substrate; and
a gate electrode formed on sidewalls of the pillar,
wherein the pillar comprises a source area, a vertical channel area over the source area, a drain area over the vertical channel area, and a leakage prevention area interposed between the vertical channel area and the drain area.
2. The vertical channel transistor of claim 1 , wherein the leakage prevention area comprises a layer containing carbon (C).
3. The vertical channel transistor of claim 1 , wherein the leakage prevention area comprises silicon carbide (SiC).
4. The vertical channel transistor of claim 1 , wherein the drain area comprises silicon.
5. The vertical channel transistor of claim 1 , wherein the drain area comprises single crystalline silicon.
6. A method for fabricating a vertical channel transistor, comprising:
forming a pillar over a substrate; and
forming a gate electrode on sidewalls of the pillar,
wherein the pillar comprises a source area, a vertical channel area over the source area, a leakage prevention area over the vertical channel area, and a drain area.
7. The method of claim 6 , wherein the forming of the pillar comprises:
forming a pillar pattern by etching the substrate;
forming a leakage prevention area at an upper part of the pillar pattern;
forming a silicon layer over the leakage prevention area; and
forming a drain area and a source area by ion-implanting impurities into the silicon layer and a lower part of the pillar pattern.
8. The method of claim 7 , wherein the forming of the leakage prevention area comprises performing ion implantation with a target set to a predetermined depth from the surface of the pillar pattern.
9. The method of claim 7 , wherein the forming of the leakage prevention area comprises performing ion implantation on the surface of the pillar pattern.
10. The method of claim 7 , wherein the forming of the leakage prevention area comprises performing epitaxial growth over the pillar pattern.
11. The method of claim 7 , wherein the forming of the silicon layer comprises performing epitaxial growth over the leakage prevention area.
12. The method of claim 6 , wherein the forming of the pillar comprises:
forming a leakage prevention area over the substrate;
forming a silicon layer over the leakage prevention area;
forming the pillar by etching the leakage prevention area, the silicon layer, and the substrate; and
forming a drain area and a source area by ion-implanting impurities into the silicon layer and a lower part of the pillar.
13. The method of claim 12 , wherein the forming of the leakage prevention area comprises performing ion implantation with a target set to a predetermined depth from the substrate surface.
14. The method of claim 12 , wherein the forming of the leakage prevention area comprises performing ion implantation on the substrate surface.
15. The method of claim 12 , wherein the forming of the leakage prevention area comprises performing epitaxial growth on the substrate.
16. The method of claim 12 , wherein the forming of the silicon layer comprises performing epitaxial growth on the leakage prevention area.
17. The method of claim 6 , wherein the leakage prevention area comprises a layer containing carbon.
18. The method of claim 6 , wherein the leakage prevention area comprises SiC.
19. A semiconductor device comprises:
a pillar formed over a substrate including a buried bit line;
a gate electrode formed on sidewalls of the pillar; and
a capacitor connected to a drain area of the pillar,
wherein the pillar comprises a source area connected to the buried bit line, a vertical channel area over the source area, a leakage prevention area over the vertical channel area, and a drain area over the leakage prevention area.
20. The semiconductor device of claim 19 , wherein the leakage prevention area comprises a layer containing carbon.
21. The semiconductor device of claim 19 , wherein the leakage prevention area comprises SiC.