Clock circuit for a microprocessor
View Patent ↗A mobile communication device includes an analog clock and a digital clock circuit. The analog clock circuit is configured to generate an oscillating output. The digital clock circuit is configured to generate a digital clock output having a frequency that is substantially equal to the frequency of the oscillating output.
1. An electronic device comprising:
a first clock circuit configured to generate a first clock output at a first frequency;
a second clock circuit configured to generate a second clock output at a second frequency that is substantially equal to the first frequency; and
a controller configured to selectively enable only one of the clock outputs at a time to provide a clock signal;
wherein the electronic device is a wireless communication device, the first clock output is enabled as the clock signal when the communication device is transmitting, and the second clock output is enabled as the clock signal when the communication device is not transmitting, such that a change from enabling the first clock to enabling the second clock is performed in response to the device changing from transmitting to not transmitting, and a change from enabling the second clock to enabling the first clock is performed in response to the device changing from not transmitting to transmitting.
2. The electronic device of claim 1 wherein the selectively enabling is by the controller selectively enabling only one of the clock circuits at a time.
3. The electronic device of claim 1 wherein the selectively enabling is by the controller enabling a selected one of the clock circuits when disabling the other clock circuit.
4. The electronic device of claim 1 wherein the controller has an input line into which both the first clock output and the second clock output are directly fed.
5. The electronic device of claim 1 wherein the selectively enabling is timed to coincide with a rising or falling edge of a timing signal, the timing signal having a frequency greater than the frequency of the first clock output.
6. The electronic device of claim 1 wherein the first and second clock circuits are respectively an analog clock circuit and a digital clock circuit.
7. The electronic device of claim 6 wherein the digital clock circuit is generated by counting cycles of a timing signal that has a frequency that is greater than the second frequency, and changing a signal level of the digital clock output after a predetermined number of cycles.