IP Library Granted Patent US 9,081,630
Granted Patent B2
US 9,081,630 · App. 13/712,496 · Granted Jul 14, 2015

Hardware-implemented semaphore for resource access based on presence of a memory buffer in a memory pool

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Quick Facts
Patent No.
US 9,081,630
App. No.
13/712,496
Granted
Jul 14, 2015
Kind
B2
Abstract

A method includes receiving a request to access a resource; determining a presence of a memory buffer in a hardware-assisted memory pool; and determining a response to the request to access the resource based on the presence of the memory buffer. A system includes a plurality of processors, a resource, and a hardware-assisted memory pool including a memory buffer; one of the plurality of processors receives a request to access the resource, determines a presence of the memory buffer, and determines a response to the request to access the resource based on the presence of the memory buffer.

Claims (31)

1. A method, comprising:

receiving a request to access a resource;

determining a presence of a memory buffer in a hardware-assisted memory pool;

determining a response to the request to access the resource based on the presence of the memory buffer, wherein the response is one of denying access to the resource based the memory buffer not being present in the hardware-assisted memory pool and allowing access to the resource based on the memory buffer being present in the hardware-assisted memory pool;

responsive to determining that the memory buffer is present in the hardware-assisted memory pool, allowing access to the resource and removing the memory buffer from the hardware-assisted memory pool; and

responsive to receiving an indication that the access to the resource is complete, releasing the memory buffer to the hardware-assisted memory pool.

2. The method of claim 1 , wherein the resource is capable of access by a single taker.

3. The method of claim 2 , wherein the hardware-assisted memory pool includes one memory buffer.

4. The method of claim 1 , wherein the resource and the hardware-assisted memory pool are elements of a multi-processor computing system.

5. The method of claim 1 , wherein the resource is capable of access by a plurality of simultaneous takers.

6. The method of claim 5 , wherein the hardware-assisted memory pool includes a plurality of memory buffers, a quantity of the plurality of memory buffers being equal to a quantity of the plurality of simultaneous takers.

7. The method of claim 1 , wherein the resource is one of a port, a device, a network interface, an input/output interface, and a data storage element.

8. A system, comprising:

a plurality of processors;

a resource; and

a hardware-assisted memory pool including a memory buffer, wherein one of the plurality of processors:

receives a request to access the resource;

determines a presence of the memory buffer;

determines a response to the request to access the resource based on the presence of the memory buffer, wherein the response is one of denying access to the resource based the memory buffer not being present in the hardware-assisted memory pool and allowing access to the resource based on the memory buffer being present in the hardware-assisted memory pool;

responsive to determining that the memo buffer is present in the hardware-assisted memory pool, allows access to the resource and removes the memory buffer from the hardware-assisted memory pool; and

responsive to receiving an indication that the access to the resource is complete, releases the memory buffer to the hardware-assisted memory pool.

9. The system of claim 8 , wherein the resource is capable of access by a single taker.

10. The system of claim 8 , wherein the resource is capable of access by a plurality of simultaneous takers.

11. The system of claim 10 , wherein the hardware-assisted memory pool includes a plurality of memory buffers, a quantity of the plurality of memory buffers being equal to a quantity of the plurality of simultaneous takers.

12. The system of claim 8 , wherein the resource is one of a port, a device, a network interface, an input/output interface, and a data storage element.

13. A non-transitory computer-readable storage medium including a set of instructions that is executable by a processor to cause the processor to perform operations comprising:

receiving a request to access a resource;

determining a presence of a memory buffer in a hardware-assisted memory pool;

determining a response to the request to access the resource based on the presence of the memory buffer, wherein the response is one of denying access to the resource based the memory buffer not being present in the hardware-assisted memory pool and allowing access to the resource based on the memory buffer being present in the hardware-assisted memory pool;

responsive to determining that the memory buffer is present in the hardware-assisted memory pool, allowing access to the resource and removing the memory buffer from the hardware-assisted memory pool; and

responsive to receiving an indication that the access to the resource is complete, releasing the memory buffer to the hardware-assisted memory pool.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Dec 28, 2022
From: GUGGENHEIM CORPORATE FUNDING, LLC
To: WIND RIVER SYSTEMS, INC.
Reel/Frame 062239/0590 →
PATENT SECURITY AGREEMENT Recorded Dec 24, 2018
From: WIND RIVER SYSTEMS, INC.
To: GUGGENHEIM CORPORATE FUNDING, LLC
Reel/Frame 049148/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2013
From: CARLSTEDT, MARKUS; JONSSON, KENNETH; MENDEL, RIKARD
To: WIND RIVER SYSTEMS, INC.
Reel/Frame 029760/0555 →