Delay circuit and semiconductor apparatus including the same
View Patent ↗A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.
1. A semiconductor apparatus comprising:
a clock delay line configured to delay an input clock and generate a delayed clock;
a command delay line configured to delay a command signal and generate a delayed command signal;
a delay line control block configured to generate a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock;
a shared shift register block configured to set delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal;
a clock driver configured to buffer the delayed clock and generate a data clock; and
an output enable signal generation unit configured to generate an output enable signal for an data output operation, based on the delayed command signal, the delayed clock and CAS latency information,
wherein the semiconductor apparatus outputs data in synchronization with the output enable signal and the delayed clock.
2. The semiconductor apparatus according to claim 1 , wherein each of the clock delay line and the command delay line comprises a plurality of unit delay cells, and a delay amount of each of the input clock and the command signal is set according to the number of unit delay cells which are enabled among the plurality of unit delay cells.
3. The semiconductor apparatus according to claim 2 , wherein the shared shift register block generates delay control signals which control whether to enable the plurality of unit delay cells, in response to the control signal.
4. The semiconductor apparatus according to claim 2 , wherein the shared shift register block increases or decreases one by one the number of the enabled unit delay cells in response to the control signal.
5. The semiconductor apparatus according to claim 1 ,
wherein the shared shift register block comprises a plurality of shift registers,
wherein the shift registers generate the delay control signals to set the delay amounts of the clock delay line and the command delay line, in response to the control signal, and
wherein the shift registers change logic values of the delay control signals when the control signal is enabled and retain logic values of the delay control signals when the control signal is disabled.
6. The semiconductor apparatus according to claim 5 , wherein the shift registers comprise:
sink drivers configured to respectively change levels of the delay control signals in response to the control signal; and
control latch parts configured to change or retain levels of the delay control signals in response to the control signal.
7. The semiconductor apparatus according to claim 6 , wherein the control latch parts do not perform a latching operation when the levels of the delay control signals are changed in response to the control signal.
8. The semiconductor apparatus according to claim 6 , wherein the shift registers are connected with respectively corresponding unit delay cells of the clock delay line and the command delay line in common.
9. The semiconductor apparatus according to claim 5 , wherein the control signal comprises:
a first odd control signal;
a second odd control signal;
a first even control signal;
a second even control signal; and
wherein the shift registers alternately receive the first and second odd control signals, and the first and second even control signals for sequentially changing the logic values of the delay control signals.
10. A semiconductor apparatus comprising:
a clock delay line configured to delay an input clock in response to delay control signals and generate a delayed clock;
a command delay line configured to delay a command signal in response to the delay control signals and generate a delayed command signal;
a delay line control block configured to generate a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock;
a shared shift register block configured to generate the delay control signals in response to the control signal and provide the delay control signals commonly to the clock delay line and the command delay line;
a clock driver configured to buffer the delayed clock and generate a data clock; and
an output enable signal generation unit configured to generate an output enable signal for an data output operation, based on the delayed command signal, the delayed clock and CAS latency information,
wherein the semiconductor apparatus outputs data in synchronization with the output enable signal and the delayed clock.
11. The semiconductor apparatus according to claim 10 , wherein each of the clock delay line and the command delay line comprises a plurality of unit delay cells, and the delay control signals control the number of unit delay cells which are enabled among the plurality of unit delay cells.
12. The semiconductor apparatus according to claim 11 , wherein the shared shift register block increases or decreases one by one the number of the enabled unit delay cells in response to the control signal.
13. The semiconductor apparatus according to claim 10 ,
wherein the shared shift register block comprises a plurality of shift registers, and
wherein the shift registers generate the delay control signals in response to the control signal, and change logic values of the delay control signals when the control signal is enabled and retain logic values of the delay control signals when the control signal is disabled.
14. The semiconductor apparatus according to claim 10 ,
wherein the shared shift register block comprises a plurality of shift registers, and
wherein the shift registers comprise:
sink drivers configured to respectively change levels of the delay control signals in response to the control signal; and
control latch parts configured to change or retain levels of the delay control signals in response to the control signal.
15. The semiconductor apparatus according to claim 14 , wherein the control latch parts do not perform a latching operation when the levels of the delay control signals are changed in response to the control signal.