Integrated visible and infrared imager devices and associated methods
Semiconductor devices having three dimensional (3D) architectures and methods form making such devices are provided. In one aspect, for example, a method for making a semiconductor device can include forming a device layer on a front side of a semiconductor layer that is substantially defect free, bonding a carrier substrate to the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a smart substrate to the processed surface. In some aspects, the method can also include removing the carrier substrate from the semiconductor layer to expose the device layer.
1. A method for making a semiconductor device, comprising:
forming a device layer on a front side of a semiconductor layer, wherein the semiconductor layer is at least substantially defect free;
bonding a carrier substrate to the device layer;
processing the semiconductor layer on a back side opposite the device layer to form a processed surface; and
coupling a bolometer to the processed surface.
2. The method of claim 1 , further comprising removing the carrier substrate to expose the device layer.
3. The method of claim 1 , wherein processing the semiconductor layer on the back side to form the processed surface further includes exposing contact pads associated with the device layer.
4. The method of claim 1 , wherein forming the device layer further includes forming optoelectronic circuitry on the front side of the semiconductor layer.
5. The method of claim 1 , wherein forming the device layer further includes forming on the front side of the semiconductor layer a member selected from the group consisting of CMOS circuitry, imaging devices, RF circuitry, photovoltaic circuitry, or a combination thereof.
6. The method of claim 1 , wherein forming the device layer further includes forming a CMOS imager.
7. The method of claim 1 , wherein the semiconductor layer includes a silicon material.
8. The method of claim 7 , wherein the silicon material is a single crystal silicon wafer.
9. The method of claim 1 , wherein processing the semiconductor layer on the back side further includes thinning the semiconductor layer from the back side to expose the device layer.
10. The method of claim 9 , wherein processing the semiconductor layer on the back side further includes implant and/or laser anneal conditions to reduce surface defects.
11. The method of claim 1 , wherein at least one of forming the device layer and processing the semiconductor layer includes forming a textured region thereon.
12. The method of claim 11 , wherein forming the textured region includes texturing with a short pulse duration laser to create surface features.
13. The method of claim 1 , further comprising forming at least one shallow or deep trench isolation in the processed surface prior to coupling the bolometer to the processed surface.
14. The method of claim 1 , further comprising forming at least one via in the processed surface prior to coupling the bolometer to the processed surface.
15. The method of claim 1 , further comprising forming backside circuitry at the processed surface prior to coupling the bolometer to the processed surface.
16. The method of claim 1 , wherein the coupling of the bolometer to the processed surface further includes:
depositing an etch material on the processed surface;
depositing the bolometer on the etch material; and
etching away at least a portion of the etch material to form a cavity between the bolometer and the processed surface.
17. The method of claim 1 , wherein the semiconductor device is not heated above a temperature of 450° C. following processing of the back side to form the processed surface.
18. A semiconductor device made according to claim 1 .
19. A semiconductor device, comprising:
a substantially defect-free semiconductor layer having a device layer on a front side and bolometer coupled to a processed surface on a backside of the semiconductor layer, wherein the bolometer and the processed surface are separated by a cavity, and wherein the device layer and the bolometer are functionally aligned.
20. The device of claim 19 , wherein the device layer is a CMOS imager.
21. The device of claim 20 , wherein at least one CMOS transistor is functionally shared with the bolometer.
22. The device of claim 19 , further comprising a semiconductor material having a depression and being coupled to the backside of the semiconductor layer, the depression being positioned to surround and form a cavity around the bolometer.
23. The device of claim 19 , wherein the device layer includes optoelectronic circuitry.
24. The device of claim 19 , wherein the device layer includes a member selected from the group consisting of CMOS circuitry, RF circuitry, photovoltaic circuitry, or a combination thereof.
25. The device of claim 19 , wherein the semiconductor layer includes a silicon material.
26. The device of claim 25 , wherein the silicon material is a single crystal silicon wafer.
27. The device of claim 19 , further comprising at least one trench in the processed surface.
28. The device of claim 19 , further comprising at least one via in the processed surface electrically coupling at least a portion of the device layer to at least a portion of the bolometer.