Associative list processing unit
View Patent ↗An associative list processing unit and method comprising employing a plurality of prioritized cell blocks and permitting inserts to occur in a single clock cycle if all of the cell blocks are not full.
1. An associative list processing unit comprising:
a plurality of prioritized cell blocks; and
control logic permitting inserts to occur in a single clock cycle if said unit is not full; and
wherein each cell block has a counter indicating the number of free lower priority cells; and
wherein each counter is initialized to the total number of cells with lower priority.
2. The associative list processing unit of claim 1 wherein each counter is decremented for each insert to a lower priority cell block.
3. The associative list processing unit of claim 1 wherein each counter is incremented for each delete from a lower priority cell block.
4. An associative list processing method comprising:
employing a plurality of prioritized cell blocks; and
permitting inserts to occur in a single clock cycle if all of the cell blocks are not full; and
wherein each cell block employs a counter indicating the number of free lower priority cell blocks; and
wherein each counter is initialized to the total number of cell blocks with lower priority.
5. The associative list processing method of claim 4 additionally comprising decrementing each counter for each insert to a lower priority cell block.
6. The associative list processing method of claim 4 additionally comprising incrementing each counter for each delete from a lower priority cell block.