IP Library Granted Patent US 9,363,508
Granted Patent B2
US 9,363,508 · App. 13/714,359 · Granted Jun 7, 2016

Delta QP handling in a high efficiency video decoder

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Quick Facts
Patent No.
US 9,363,508
App. No.
13/714,359
Granted
Jun 7, 2016
Kind
B2
Abstract

A system and method are provided including a deblocker processor that reads a first data load for a first processing block from a buffer. The deblocker processor holds the first data load in a storage array in response to the first data load not including a valid value for a first quantization parameter and receives a second data load for a second processing block from the buffer. In response to the second data load including a valid value for a second quantization parameter, the deblocker processor processes the first processing block based on the second quantization parameter.

Claims (20)

1. A method comprising:

by a deblocker processor:

reading a first set of parameters for a first processing block from a buffer;

determining if the first set of parameters does not include a valid quantization value for processing the first processing block;

storing the first set of parameters including transform coefficients in a storage array on the deblocker processor in response to the first set of parameters not including the valid quantization value for processing the first processing block;

operating on the first processing block by at least one of a motion compensation processor, inverse transform processor, and spatial prediction processor based on the first set of parameters stored in the storage array prior to receiving to a valid quantization value corresponding to the first processing block;

reading a subsequent set of parameters for subsequent processing blocks from the buffer; and

processing the first processing block based on a valid quantization value in the subsequent set of parameters, in response to the subsequent set of parameters including the valid quantization value for processing the first processing block.

2. The method of claim 1 further comprising processing, by the deblocker processor, a subsequent processing block based on the subsequent set of parameters in response to the subsequent set of parameters including the valid quantization value.

3. The method of claim 1 further comprising continuing processing by the deblocker processor until the subsequent sets of parameters stored in the storage array are exhausted.

4. The method of claim 1 wherein the first set of parameters includes a non-valid quantization value indicating that the valid quantization value has not yet arrived for the first processing block.

5. A system comprising:

a decoder operable to use High Efficiency Video Coding (HEVC), the decoder comprising a deblocker processor, the deblocker processor operable to:

read a first set of deblocking parameters for a first processing block from a buffer;

determine if the first set of deblocking parameters includes a quantization parameter value or a value indicating that the quantization parameter value has not yet arrived for the first processing block;

hold the first set of deblocking parameters in a storage array in response to the first set of deblocking parameters including the value indicating that the quantization parameter value has not yet arrived for the first processing block;

perform at least one of motion compensation and spatial prediction based on the first set of deblocking parameters stored in the storage array prior to receiving to a valid quantization value corresponding to the first processing block;

read a second set of deblocking parameters for a second processing block from the buffer; and

process the first and second processing blocks based on the quantization parameter value in response to the second set of deblocking parameters including the quantization parameter value.

6. The system of claim 5 wherein the storage array comprises static random access memory embedded in the deblocker processor.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2012
From: HELLMAN, TIMOTHY
To: BROADCOM CORPORATION
Reel/Frame 029477/0490 →